Lines Matching +full:bank +full:- +full:size

4 # SPDX-License-Identifier: Apache-2.0
38 	  v2 ISA for the ARC-HS & ARC-EM cores
66 	  If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
67 	  floating-point extension
73 	  If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
74 	  floating-point and double assist instructions
135 	  - LPcc instruction
136 	  - LP_COUNT core reg
137 	  - LP_START, LP_END aux regs
144 	  Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
153 	  Interrupts available will be 0 to NUM_IRQS-1.
157 	  The BSP must provide a valid default. This drives the size of the
168 	  bank. If fast interrupts are supported (FIRQ), the 2nd
169 	  register bank, in the set, will be used by FIRQ interrupts.
171 	  register bank, the fast interrupt handler must save
174 	  to use second register bank - otherwise all interrupts will use
175 	  same register bank. Such configuration isn't supported in software
187 	  other regs will be saved according to the number of register bank;
203 	int "FIRQ stack size"
207 	  The size of firq stack.
239 	  - The ARC stack checking, or
240 	  - the MPU-based stack guard
245 	  prioritized over the MPU-based stack guard.
262 	  RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization
289 	  Depending on the configuration, CPU can contain accumulator reg-pair
302 	int "SJLI table size"
306 	  The size of sjli (Secure Jump and Link Indexed) table. The
374 	int "ARC exception handling stack size"
378 	  Size in bytes of exception handling stack which is at the top of
386 	bool "Make early stage SoC-specific initialization"
388 	  Call SoC per-core setup code on early stage initialization