Lines Matching +full:bank +full:- +full:size
4 * SPDX-License-Identifier: Apache-2.0
41 #error Flash driver on M4 requires the DT property bank2-flash-size
52 /* When flash is dual bank and flash size is smaller than Max flash size of
60 int bank; member
71 if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { in write_optb()
73 return -EIO; in write_optb()
76 if ((regs->OPTCR & mask) == value) { in write_optb()
87 regs->OPTCR = (regs->OPTCR & ~mask) | value; in write_optb()
89 regs->OPTCR |= FLASH_OPTCR_PG_OPT; in write_optb()
91 regs->OPTCR |= FLASH_OPTCR_OPTSTART; in write_optb()
110 return (regs->OPTSR_CUR & FLASH_OPTSR_RDP_Msk) >> FLASH_OPTSR_RDP_Pos; in flash_stm32_get_rdp_level()
125 regs->OPTCR |= FLASH_OPTCR_OPTLOCK; in flash_stm32_option_bytes_lock()
126 } else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { in flash_stm32_option_bytes_lock()
128 regs->OPTKEYR = FLASH_OPTKEY1; in flash_stm32_option_bytes_lock()
129 regs->OPTKEYR = FLASH_OPTKEY2; in flash_stm32_option_bytes_lock()
131 regs->OPTKEYR = FLASH_OPT_KEY1; in flash_stm32_option_bytes_lock()
132 regs->OPTKEYR = FLASH_OPT_KEY2; in flash_stm32_option_bytes_lock()
155 LOG_ERR("Range ovelaps flash bank discontinuity"); in flash_stm32_valid_range()
189 sr = regs->ISR;
191 uint32_t word = regs->ECCSFADDR & FLASH_ECCSFADDR_SEC_FADD;
193 LOG_WRN("Bank%d ECC error at 0x%08x", 1,
198 uint32_t word = regs->ECCDFADDR & FLASH_ECCDFADDR_DED_FADD;
200 LOG_WRN("Bank%d ECC error at 0x%08x", 1,
205 regs->ICR = FLASH_FLAG_ECC_ERRORS;
211 sr = regs->SR1;
213 uint32_t word = regs->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR;
215 LOG_WRN("Bank%d ECC error at 0x%08x", 1,
219 regs->CCR1 = FLASH_FLAG_ALL_BANK1;
223 LOG_ERR("Status Bank%d: 0x%08x", 1, sr);
224 return -EIO;
228 sr = regs->SR2;
230 uint32_t word = regs->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR;
232 LOG_WRN("Bank%d ECC error at 0x%08x", 2,
235 regs->CCR2 = FLASH_FLAG_ALL_BANK2;
246 regs->CCR2 |= FLASH_FLAG_STRBERR_BANK2;
249 LOG_ERR("Status Bank%d: 0x%08x", 2, sr);
250 return -EIO;
264 return -EIO;
267 while ((FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW) ||
268 (FLASH_STM32_REGS(dev)->SR2 & FLASH_SR_QW))
270 while (FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW)
275 return -EIO;
292 bank_swap = (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == FLASH_OPTCR_SWAP_BANK);
295 sector.bank = 1;
296 sector.cr = ®s->CR1;
297 sector.sr = ®s->SR1;
299 sector.sector_index -= BANK2_OFFSET / FLASH_SECTOR_SIZE;
300 sector.bank = 1;
301 sector.cr = ®s->CR2;
302 sector.sr = ®s->SR2;
304 sector.bank = 2;
305 sector.cr = ®s->CR1;
306 sector.sr = ®s->SR1;
308 sector.sector_index -= BANK2_OFFSET / FLASH_SECTOR_SIZE;
309 sector.bank = 2;
310 sector.cr = ®s->CR2;
311 sector.sr = ®s->SR2;
314 sector.bank = 0;
321 sector.bank = 1;
322 sector.cr = ®s->CR1;
323 sector.sr = ®s->SR1;
326 sector.bank = 0;
340 if (sector.bank == 0) {
343 return -EINVAL;
348 return -EIO;
373 for (; address <= offset + len - 1; address += FLASH_SECTOR_SIZE) {
386 while (*(sector->sr) & FLASH_SR_QW) {
389 return -EIO;
403 if (sector.bank == 0) {
405 return -EINVAL;
410 return -EIO;
422 return -EIO;
473 for (j = 0; j < len - i; ++j) {
498 /* Bank 1 */
500 regs->CR1 |= FLASH_CR_LOCK;
502 if (regs->CR1 & FLASH_CR_LOCK) {
503 regs->KEYR1 = FLASH_KEY1;
504 regs->KEYR1 = FLASH_KEY2;
508 /* Bank 2 */
510 regs->CR2 |= FLASH_CR_LOCK;
512 if (regs->CR2 & FLASH_CR_LOCK) {
513 regs->KEYR2 = FLASH_KEY1;
514 regs->KEYR2 = FLASH_KEY2;
533 if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
548 size_t flush_len = ROUND_UP(offset + len - 1, FLASH_SECTOR_SIZE) - flush_offset;
553 return -EINVAL;
597 return -EINVAL;
628 return -EINVAL;
645 SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
652 SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
691 BANK2_OFFSET - (SECTOR_PER_BANK * FLASH_SECTOR_SIZE);
746 return -ENODEV;
750 if (clock_control_on(clk, (clock_control_subsys_t)&p->pclken) != 0) {
752 return -EIO;