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/Zephyr-latest/samples/subsys/task_wdt/boards/
Dnucleo_f091rc.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * stm32F0 has a WWDG clock by APB1 where the APB1 prescaler is 1..16
9 * Adjust the APB1 clock to match the WDG timeout.
13 /delete-property/ apb1-prescaler;
14 apb1-prescaler = <16>;
/Zephyr-latest/dts/arm/st/f3/
Dstm32f373.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/stm32f1_adc.h>
12 compatible = "st,stm32f373", "st,stm32f3", "simple-bus";
17 * prescaler in the RCC register
19 compatible = "st,stm32f1-rcc";
22 pinctrl: pin-controller@48000000 {
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
33 compatible = "st,stm32-i2c-v2";
[all …]
/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xg.dtsi1 /* SPDX-License-Identifier: Apache-2.0
18 flash-controller@40022000 {
22 * This matters if you're doing in-application
24 * read-while-write capabilities, but is
25 * otherwise a non-issue.
28 erase-block-size = <DT_SIZE_K(2)>;
33 compatible = "st,stm32-timers";
39 st,prescaler = <0>;
43 compatible = "st,stm32-pwm";
45 #pwm-cells = <3>;
[all …]
Dstm32f103Xc.dtsi2 * Copyright (c) 2017 I-SENSE group of ICCS
7 * SPDX-License-Identifier: Apache-2.0
19 flash-controller@40022000 {
22 erase-block-size = <DT_SIZE_K(2)>;
27 compatible = "st,stm32-uart";
29 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
30 resets = <&rctl STM32_RESET(APB1, 19U)>;
36 compatible = "st,stm32-uart";
38 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
39 resets = <&rctl STM32_RESET(APB1, 20U)>;
[all …]
Dstm32f105.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
12 /delete-node/ pll;
15 #clock-cells = <0>;
16 compatible = "st,stm32f105-pll-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32f105-pll2-clock";
29 compatible = "st,stm32f105", "st,stm32f1", "simple-bus";
31 flash-controller@40022000 {
33 erase-block-size = <DT_SIZE_K(2)>;
[all …]
/Zephyr-latest/dts/arm/st/l0/
Dstm32l071.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l071", "st,stm32l0", "simple-bus";
13 pinctrl: pin-controller@50000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
24 compatible = "st,stm32-i2c-v2";
25 clock-frequency = <I2C_BITRATE_STANDARD>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f405.dtsi5 * SPDX-License-Identifier: Apache-2.0
16 compatible = "st,stm32f405", "st,stm32f4", "simple-bus";
18 pinctrl: pin-controller@40020000 {
22 compatible = "st,stm32-gpio";
23 gpio-controller;
24 #gpio-cells = <2>;
30 compatible = "st,stm32-gpio";
31 gpio-controller;
32 #gpio-cells = <2>;
38 compatible = "st,stm32-gpio";
[all …]
Dstm32f412.dtsi2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &dac1;
10 /delete-node/ &rng;
15 #clock-cells = <0>;
16 compatible = "st,stm32f411-plli2s-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32-clock-mux";
29 compatible = "st,stm32f412", "st,stm32f4", "simple-bus";
31 pinctrl: pin-controller@40020000 {
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
Dst,stm32mp1-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 clock-frequency (mlhclk_ck).
10 compatible: "st,stm32mp1-rcc"
13 - name: st,stm32-rcc.yaml
14 property-blocklist:
15 - ahb-prescaler
16 - apb1-prescaler
17 - apb2-prescaler
18 - undershoot-prevention
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
[all …]
/Zephyr-latest/dts/arm/st/f0/
Dstm32f070Xb.dtsi4 * SPDX-License-Identifier: Apache-2.0
15 flash-controller@40022000 {
17 erase-block-size = <2048>;
23 * USARTs 3-4 share the same IRQ on stm32f070Xb devices. This
29 compatible = "st,stm32-usart", "st,stm32-uart";
31 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
32 resets = <&rctl STM32_RESET(APB1, 18U)>;
38 compatible = "st,stm32-usart", "st,stm32-uart";
40 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
41 resets = <&rctl STM32_RESET(APB1, 19U)>;
[all …]
Dstm32f051.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32f051", "st,stm32f0", "simple-bus";
14 compatible = "st,stm32-usart", "st,stm32-uart";
16 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
17 resets = <&rctl STM32_RESET(APB1, 17U)>;
23 compatible = "st,stm32-i2c-v2";
24 clock-frequency = <I2C_BITRATE_STANDARD>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
[all …]
Dstm32f030X8.dtsi4 * SPDX-License-Identifier: Apache-2.0
15 flash-controller@40022000 {
22 compatible = "st,stm32-usart", "st,stm32-uart";
24 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
25 resets = <&rctl STM32_RESET(APB1, 17U)>;
31 compatible = "st,stm32-i2c-v2";
32 clock-frequency = <I2C_BITRATE_STANDARD>;
33 #address-cells = <1>;
34 #size-cells = <0>;
36 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
/Zephyr-latest/dts/arm/st/l4/
Dstm32l471.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l471", "st,stm32l4", "simple-bus";
13 pinctrl: pin-controller@48000000 {
16 compatible = "st,stm32-gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
32 compatible = "st,stm32-gpio";
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/
Dhse_32.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(32)>;
19 ahb-prescaler = <1>;
20 ahb5-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hse-div2;
19 clock-frequency = <DT_FREQ_M(16)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16_ahb5_div.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 ahb5-div;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb7-prescaler = <1>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb3-prescaler = <1>;
/Zephyr-latest/tests/drivers/watchdog/wdt_basic_api/boards/
Dstm32_wwdg.overlay4 * SPDX-License-Identifier: Apache-2.0
8 /* Reduce APB1 speed to achieve test window timings */
9 apb1-prescaler = <16>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dcsi4.overlay5 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(4)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb3-prescaler = <1>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f7_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
[all …]

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