Lines Matching +full:apb1 +full:- +full:prescaler
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
12 /delete-node/ pll;
15 #clock-cells = <0>;
16 compatible = "st,stm32f105-pll-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32f105-pll2-clock";
29 compatible = "st,stm32f105", "st,stm32f1", "simple-bus";
31 flash-controller@40022000 {
33 erase-block-size = <DT_SIZE_K(2)>;
38 compatible = "st,stm32-bxcan";
41 interrupt-names = "TX", "RX0", "RX1", "SCE";
42 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
47 compatible = "st,stm32-bxcan";
50 interrupt-names = "TX", "RX0", "RX1", "SCE";
52 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
57 compatible = "st,stm32-dac";
59 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
61 #io-channel-cells = <1>;
65 compatible = "st,stm32-uart";
67 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
68 resets = <&rctl STM32_RESET(APB1, 19U)>;
74 compatible = "st,stm32-uart";
76 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
77 resets = <&rctl STM32_RESET(APB1, 20U)>;
83 compatible = "st,stm32-spi";
84 #address-cells = <1>;
85 #size-cells = <0>;
87 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
93 compatible = "st,stm32-spi";
94 #address-cells = <1>;
95 #size-cells = <0>;
97 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
103 compatible = "st,stm32-timers";
105 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
106 resets = <&rctl STM32_RESET(APB1, 3U)>;
108 interrupt-names = "global";
109 st,prescaler = <0>;
113 compatible = "st,stm32-pwm";
115 #pwm-cells = <3>;
120 compatible = "st,stm32-timers";
122 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
123 resets = <&rctl STM32_RESET(APB1, 4U)>;
125 interrupt-names = "global";
126 st,prescaler = <0>;
131 compatible = "st,stm32-timers";
133 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
134 resets = <&rctl STM32_RESET(APB1, 5U)>;
136 interrupt-names = "global";
137 st,prescaler = <0>;
142 compatible = "st,stm32-otgfs";
145 interrupt-names = "otgfs";
146 num-bidir-endpoints = <4>;
147 ram-size = <1280>;
155 compatible = "usb-nop-xceiv";
156 #phy-cells = <0>;