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/Zephyr-latest/tests/drivers/can/host/pytest/
Dconftest.py3 # SPDX-License-Identifier: Apache-2.0
13 from can import Bus, BusABC
19 def pytest_addoption(parser) -> None:
21 parser.addoption('--can-context', default=None,
22 help='Configuration context to use for python-can (default: None)')
25 def fixture_context(request, dut: DeviceAdapter) -> str:
26 """Return the name of the python-can configuration context to use."""
27 ctx = request.config.getoption('--can-context')
35 logger.info('using python-can configuration context "%s"', ctx)
39 def fixture_chosen(shell: Shell) -> str:
[all …]
Dcan_shell.py3 # SPDX-License-Identifier: Apache-2.0
6 Zephyr CAN shell module support for providing a python-can bus interface for testing.
21 class CanShellBus(BusABC): # pylint: disable=abstract-method
27 can_filters: Optional[CanFilters] = None, **kwargs) -> None:
52 def _get_capabilities(self) -> list[str]:
58 m = regex_compiled.match(line)
59 if m:
60 return m.group('caps').split()
64 def _set_mode(self, mode: str) -> None:
79 def send(self, msg: Message, timeout: Optional[float] = None) -> None:
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/Zephyr-latest/drivers/clock_control/
Dclock_control_npcm.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
32 /* 0x002: HFCG M Low Byte Value */
35 /* 0x004: HFCG M High Byte Value */
44 /* 0x010: HFCG Bus Clock Dividers */
47 /* 0x012: HFCG Bus Clock Dividers */
50 /* 0x014: HFCG Bus Clock Dividers */
53 /* 0x01d: HFCG Bus Clock Dividers */
57 /* clock bus references */
91 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
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/Zephyr-latest/dts/arm/
Darmv8.1-m.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "simple-bus";
14 interrupt-parent = <&nvic>;
17 nvic: interrupt-controller@e000e100 {
18 #address-cells = <1>;
19 compatible = "arm,v8.1m-nvic";
21 interrupt-controller;
22 #interrupt-cells = <2>;
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/Zephyr-latest/samples/sensor/icm42605/
DREADME.rst1 .. zephyr:code-sample:: icm42605
3 :relevant-api: sensor_interface
20 overlay must be provided to identify the SPI bus and GPIO used to
29 .. zephyr-app-commands::
30 :zephyr-app: samples/sensor/icm42605
37 .. code-block:: console
39 *** Booting Zephyr OS build zephyr-v2.1.0-576-g4b38659b0661 ***
41 accel -5.882554 -6.485893 5.868188 m/s/s
42 gyro 0.014522 0.002264 -0.036905 rad/s
44 accel -5.841853 -6.435615 5.911283 m/s/s
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/Zephyr-latest/samples/sensor/mpu6050/
DREADME.rst1 .. zephyr:code-sample:: mpu6050
3 :relevant-api: sensor_interface
22 overlay must be provided to identify the I2C bus and GPIO used to
31 .. zephyr-app-commands::
32 :zephyr-app: samples/sensor/mpu6050
39 .. code-block:: console
41 *** Booting Zephyr OS build zephyr-v2.1.0-576-g4b38659b0661 ***
43 accel -5.882554 -6.485893 5.868188 m/s/s
44 gyro 0.014522 0.002264 -0.036905 rad/s
46 accel -5.841853 -6.435615 5.911283 m/s/s
[all …]
/Zephyr-latest/samples/sensor/6dof_motion_drdy/
DREADME.rst1 .. zephyr:code-sample:: 6dof_motion_drdy
3 :relevant-api: sensor_interface
5 Get 6-Axis accelerometer and gyroscope data from a sensor (data ready interrupt mode).
10 This sample application periodically (100 Hz) measures the 6-axis IMU sensor with
19 overlay must be provided to identify the 6-axis motion sensor, the SPI or I2C bus interface and the…
25 This sample supports up to 6-Axis IMU devices. Each device needs
26 to be aliased as ``6dof-motion-drdyN`` where ``N`` goes from ``0`` to ``9``. For example:
28 .. code-block:: devicetree
32 6dof-motion-drdy0 = &icm42670p;
38 .. zephyr-app-commands::
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/Zephyr-latest/dts/bindings/gpio/
Dm5stack,mbus-header.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on M5Stack M-Bus headers.
26 compatible: "m5stack,mbus-header"
28 include: [gpio-nexus.yaml, base.yaml]
/Zephyr-latest/arch/x86/core/
Dpcie.c4 * SPDX-License-Identifier: Apache-2.0
39 struct acpi_mcfg *m = acpi_table_get("MCFG", 0); in pcie_mm_init() local
41 if (m != NULL) { in pcie_mm_init()
42 int n = (m->header.Length - sizeof(*m)) / sizeof(m->pci_segs[0]); in pcie_mm_init()
48 bus_segs[i].start_bus = m->pci_segs[i].StartBusNumber; in pcie_mm_init()
50 1 + m->pci_segs[i].EndBusNumber - m->pci_segs[i].StartBusNumber; in pcie_mm_init()
52 phys_addr = m->pci_segs[i].Address; in pcie_mm_init()
53 /* 32 devices & 8 functions per bus, 4k per device */ in pcie_mm_init()
69 int off = PCIE_BDF_TO_BUS(bdf) - bus_segs[i].start_bus; in pcie_mm_conf()
95 #define PCIE_X86_CAP_WORD_MASK 0x3FU /* 6-bit word index .. */
[all …]
/Zephyr-latest/drivers/lora/
Dsx126x.c5 * SPDX-License-Identifier: Apache-2.0
43 .bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8) | SPI_TRANSFER_MSB, 0),
59 #define MODE(m) [MODE_##m] = #m argument
72 static const char *sx126x_mode_name(RadioOperatingModes_t m) in sx126x_mode_name() argument
76 if (m < ARRAY_SIZE(mode_names) && mode_names[m]) { in sx126x_mode_name()
77 return mode_names[m]; in sx126x_mode_name()
125 ret = spi_write_dt(&dev_config.bus, &tx); in sx126x_spi_transceive()
127 ret = spi_transceive_dt(&dev_config.bus, &tx, &rx); in sx126x_spi_transceive()
196 LOG_DBG("-> status: 0x%" PRIx8, rx_req[1]); in SX126xReadCommand()
391 ret = spi_write_dt(&dev_config.bus, &tx); in SX126xWakeup()
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/Zephyr-latest/boards/arm/mps2/
DKconfig.defconfig2 # SPDX-License-Identifier: Apache-2.0
39 # MPU-based null-pointer dereferencing detection cannot
40 # be applied as the (0x0 - 0x400) is unmapped but QEMU
41 # will still permit bus access.
48 # By default, if we build for a Non-Secure version of the board,
49 # force building with TF-M as the Secure Execution Environment.
/Zephyr-latest/include/zephyr/arch/arm/cortex_m/
Dmemory_map.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief ARM CORTEX-M memory map
11 * This module contains definitions for the memory map of the CORTEX-M series of
20 /* 0x00000000 -> 0x1fffffff: Code in ROM [0.5 GB] */
24 /* 0x20000000 -> 0x3fffffff: SRAM [0.5GB] */
32 /* 0x40000000 -> 0x5fffffff: Peripherals [0.5GB] */
40 /* 0x60000000 -> 0x9fffffff: external RAM [1GB] */
44 /* 0xa0000000 -> 0xdfffffff: external devices [1GB] */
48 /* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
50 /* 0xe0000000 -> 0xe00fffff: private peripheral bus */
[all …]
/Zephyr-latest/soc/atmel/sam/samv71/
Dsoc_config.c3 * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
26 * by Bus Matrix in atmel_samv71_config()
28 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; in atmel_samv71_config()
31 /* In Cortex-M based SoCs JTAG interface can be used to perform in atmel_samv71_config()
36 /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix in atmel_samv71_config()
38 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; in atmel_samv71_config()
42 PMC->PMC_SCDR = PMC_SCDR_PCK3; in atmel_samv71_config()
43 while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { in atmel_samv71_config()
47 PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; in atmel_samv71_config()
[all …]
/Zephyr-latest/soc/atmel/sam/same70/
Dsoc_config.c4 * SPDX-License-Identifier: Apache-2.0
26 * by Bus Matrix in atmel_same70_config()
28 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; in atmel_same70_config()
31 /* In Cortex-M based SoCs JTAG interface can be used to perform in atmel_same70_config()
36 /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */ in atmel_same70_config()
37 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; in atmel_same70_config()
41 PMC->PMC_SCDR = PMC_SCDR_PCK3; in atmel_same70_config()
42 while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { in atmel_same70_config()
46 PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; in atmel_same70_config()
48 PMC->PMC_SCER = PMC_SCER_PCK3; in atmel_same70_config()
[all …]
/Zephyr-latest/doc/build/dts/
Dzephyr_dt_i2c_high_level.svg1 <?xml version="1.0" encoding="UTF-8"?>
2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
3 …-color: rgb(255, 255, 255);" xmlns:xlink="http://www.w3.org/1999/xlink" version="1.1" width="429px…
/Zephyr-latest/dts/bindings/clock/
Dst,stm32h7rs-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
15 Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7rs-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
52 - 1
[all …]
Dst,stm32h7-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
15 Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
52 - 1
[all …]
/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
68 bool "SPI flash operates full-duplex with fast reading mode"
102 bool "SPI flash size 1M Bytes"
104 The SPI flash size is 1M Bytes.
107 bool "SPI flash size 2M Bytes"
109 The SPI flash size is 2M Bytes.
112 bool "SPI flash size 4M Bytes"
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc2520.c1 /* ieee802154_cc2520.c - TI CC2520 driver */
8 * SPDX-License-Identifier: Apache-2.0
47 * 1 - Debug related functions
48 * 2 - Generic helper functions (for any parts)
49 * 3 - GPIO related functions
50 * 4 - TX related helper functions
51 * 5 - RX related helper functions
52 * 6 - Radio device API functions
53 * 7 - Legacy radio device API functions
54 * 8 - Initialization
[all …]
/Zephyr-latest/arch/arm/include/cortex_m/
Dexception.h2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Exception/interrupt context helpers for Cortex-M CPUs
68 * integer only stack frame or an extended floating-point stack frame.
82 /* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or
83 * Non-secure stack is used to restore stack frame on exception return.
108 * - The function shall only be called from ISR context.
109 * - We do not use ARM processor state flags to determine
121 return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false); in arch_is_in_nested_exception()
154 * for Cortex-M variants without BASEPRI (e.g. ARMv6-M). in z_arm_exc_setup()
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/Zephyr-latest/soc/nxp/imx/imx6sx/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
94 /* Set access to I2C-1 for M4 core */ in SOC_RdcInit()
98 /* Set access to I2C-2 for M4 core */ in SOC_RdcInit()
102 /* Set access to I2C-3 for M4 core */ in SOC_RdcInit()
106 /* Set access to I2C-4 for M4 core */ in SOC_RdcInit()
111 /* Set access to PWM-1 for M4 core */ in SOC_RdcInit()
115 /* Set access to PWM-2 for M4 core */ in SOC_RdcInit()
119 /* Set access to PWM-3 for M4 core */ in SOC_RdcInit()
123 /* Set access to PWM-4 for M4 core */ in SOC_RdcInit()
[all …]
/Zephyr-latest/arch/arm/core/cortex_m/
DKconfig1 # ARM Cortex-M platform configuration options
3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
10 # if one select a different ARM Cortex Family (Cortex-A or Cortex-R)
17 This option signifies the use of a Cortex-M0 CPU
24 This option signifies the use of a Cortex-M0+ CPU
31 This option signifies the use of a Cortex-M1 CPU
38 This option signifies the use of a Cortex-M3 CPU
46 This option signifies the use of a Cortex-M4 CPU
54 This option signifies the use of a Cortex-M23 CPU
[all …]
/Zephyr-latest/boards/norik/octopus_io_board/doc/
Dindex.rst6 Octopus IO-Board is an expansion to the Octopus SoM, which is built around the nRF9160 SiP
7 offering NB-IoT and LTE-M connectivity, GPS and accelerometer. Octopus IO-Board expands
9 development and prototyping of low-power IoT applications.
11 nRF9160 SiP contains ARM Cortex-M33 application processor and the
18 * :abbr:`I2C (Inter-Integrated Circuit)`
25 * :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)`
29 Octopus IO-Board offers the following features:
32 * USB-C for power
41 * Tag-Connect TC2030-IDC 6-pin connector for SWD programming and debugging
44 More information about the board can be found at the `Octopus IO-Board Product Page`_
[all …]
/Zephyr-latest/boards/toradex/verdin_imx8mp/doc/
Dindex.rst7 i.MX 8M Plus family of processors (or System on Chips - SoCs).
11 +-------------------------------------------------+-----------------------+
14 | Verdin iMX8M Plus Quad 8GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
15 +-------------------------------------------------+-----------------------+
16 | Verdin iMX8M Plus Quad 4GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
17 +-------------------------------------------------+-----------------------+
18 | Verdin iMX8M Plus Quad 4GB IT | i.MX 8M Plus Quad |
19 +-------------------------------------------------+-----------------------+
20 | Verdin iMX8M Plus Quad 2GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
21 +-------------------------------------------------+-----------------------+
[all …]
/Zephyr-latest/boards/native/nrf_bsim/doc/
Dnrf54l15bsim.rst48 * GRTC (Global Real-time Counter)
79 TrustZone, TF-M and other security considerations
84 * There is no differentiation between secure and non secure execution states or bus accesses.
88 and non-secure images.
91 * TF-M cannot be used.
95 As entropy driver, the :dtcompatible:`zephyr,native-posix-rng` is enabled by default.

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