Lines Matching +full:m +full:- +full:bus

2 # SPDX-License-Identifier: Apache-2.0
14   "clock-frequency" property.
15   Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
20            clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29   Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
33 include: [clock-controller.yaml, base.yaml]
39   "#clock-cells":
42   clock-frequency:
52       - 1
54         D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
66       - 1
67       - 2
68       - 4
69       - 8
70       - 16
71       - 64
72       - 128
73       - 256
74       - 512
82       - 1
83       - 2
84       - 4
85       - 8
86       - 16
94       - 1
95       - 2
96       - 4
97       - 8
98       - 16
106       - 1
107       - 2
108       - 4
109       - 8
110       - 16
118       - 1
119       - 2
120       - 4
121       - 8
122       - 16
124 clock-cells:
125   - bus
126   - bits