4  * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
94 	/* Set access to I2C-1 for M4 core */  in SOC_RdcInit()
98 	/* Set access to I2C-2 for M4 core */  in SOC_RdcInit()
102 	/* Set access to I2C-3 for M4 core */  in SOC_RdcInit()
106 	/* Set access to I2C-4 for M4 core */  in SOC_RdcInit()
111 	/* Set access to PWM-1 for M4 core */  in SOC_RdcInit()
115 	/* Set access to PWM-2 for M4 core */  in SOC_RdcInit()
119 	/* Set access to PWM-3 for M4 core */  in SOC_RdcInit()
123 	/* Set access to PWM-4 for M4 core */  in SOC_RdcInit()
127 	/* Set access to PWM-5 for M4 core */  in SOC_RdcInit()
131 	/* Set access to PWM-6 for M4 core */  in SOC_RdcInit()
135 	/* Set access to PWM-7 for M4 core */  in SOC_RdcInit()
139 	/* Set access to PWM-8 for M4 core */  in SOC_RdcInit()
143 	/* Set access to ADC-1 for M4 core */  in SOC_RdcInit()
147 	/* Set access to ADC-2 for M4 core */  in SOC_RdcInit()
155 	/* Enable System Bus Cache */  in SOC_CacheInit()
165 	/* Enable system bus cache, enable write buffer */  in SOC_CacheInit()
169 	/* Enable Code Bus Cache */  in SOC_CacheInit()
179 	/* Enable code bus cache, enable write buffer */  in SOC_CacheInit()
188 	/* OSC/PLL is already initialized by Cortex-A9 core */  in SOC_ClockInit()
197 	/* Set UART clock is derived from OSC clock (24M) */  in SOC_ClockInit()
209 	/* Select EPIT clock is derived from OSC (24M) */  in SOC_ClockInit()
225 	/* Select I2C clock is derived from OSC (24M) */  in SOC_ClockInit()
247 	/* Select PWM clock is derived from OSC (24M) */  in SOC_ClockInit()