Lines Matching +full:m +full:- +full:bus
4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
32 /* 0x002: HFCG M Low Byte Value */
35 /* 0x004: HFCG M High Byte Value */
44 /* 0x010: HFCG Bus Clock Dividers */
47 /* 0x012: HFCG Bus Clock Dividers */
50 /* 0x014: HFCG Bus Clock Dividers */
53 /* 0x01d: HFCG Bus Clock Dividers */
57 /* clock bus references */
91 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
93 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
95 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
97 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
99 #define AHB6DIV_VAL (DT_PROP(DT_NODELABEL(pcc), ahb6_prescaler) - 1)
101 #define FIUDIV_VAL (DT_PROP(DT_NODELABEL(pcc), fiu_prescaler) - 1)
103 #define I3CDIV_VAL (DT_PROP(DT_NODELABEL(pcc), i3c_prescaler) - 1)
139 uint16_t bus; member
143 {.clock_id = NPCM_CLOCK_PWM_I, .bus = NPCM_CLOCK_BUS_LFCLK},
144 {.clock_id = NPCM_CLOCK_PWM_J, .bus = NPCM_CLOCK_BUS_LFCLK},
145 {.clock_id = NPCM_CLOCK_I3CI, .bus = NPCM_CLOCK_BUS_APB3},
146 {.clock_id = NPCM_CLOCK_UART3, .bus = NPCM_CLOCK_BUS_APB2},
147 {.clock_id = NPCM_CLOCK_UART2, .bus = NPCM_CLOCK_BUS_APB2},
149 {.clock_id = NPCM_CLOCK_FIU, .bus = NPCM_CLOCK_BUS_FIU},
150 {.clock_id = NPCM_CLOCK_USB20, .bus = NPCM_CLOCK_BUS_USB20_CLK},
151 {.clock_id = NPCM_CLOCK_UART, .bus = NPCM_CLOCK_BUS_APB2},
153 {.clock_id = NPCM_CLOCK_PWM_A, .bus = NPCM_CLOCK_BUS_LFCLK},
154 {.clock_id = NPCM_CLOCK_PWM_B, .bus = NPCM_CLOCK_BUS_LFCLK},
155 {.clock_id = NPCM_CLOCK_PWM_C, .bus = NPCM_CLOCK_BUS_LFCLK},
156 {.clock_id = NPCM_CLOCK_PWM_D, .bus = NPCM_CLOCK_BUS_LFCLK},
157 {.clock_id = NPCM_CLOCK_PWM_E, .bus = NPCM_CLOCK_BUS_LFCLK},
158 {.clock_id = NPCM_CLOCK_PWM_F, .bus = NPCM_CLOCK_BUS_LFCLK},
159 {.clock_id = NPCM_CLOCK_PWM_G, .bus = NPCM_CLOCK_BUS_LFCLK},
160 {.clock_id = NPCM_CLOCK_PWM_H, .bus = NPCM_CLOCK_BUS_LFCLK},
162 {.clock_id = NPCM_CLOCK_SMB1, .bus = NPCM_CLOCK_BUS_APB3},
163 {.clock_id = NPCM_CLOCK_SMB2, .bus = NPCM_CLOCK_BUS_APB3},
164 {.clock_id = NPCM_CLOCK_SMB3, .bus = NPCM_CLOCK_BUS_APB3},
165 {.clock_id = NPCM_CLOCK_SMB4, .bus = NPCM_CLOCK_BUS_APB3},
166 {.clock_id = NPCM_CLOCK_SMB5, .bus = NPCM_CLOCK_BUS_APB3},
167 {.clock_id = NPCM_CLOCK_SMB6, .bus = NPCM_CLOCK_BUS_APB3},
169 {.clock_id = NPCM_CLOCK_ITIM1, .bus = NPCM_CLOCK_BUS_LFCLK},
170 {.clock_id = NPCM_CLOCK_ITIM2, .bus = NPCM_CLOCK_BUS_LFCLK},
171 {.clock_id = NPCM_CLOCK_ITIM3, .bus = NPCM_CLOCK_BUS_LFCLK},
172 {.clock_id = NPCM_CLOCK_ADC, .bus = NPCM_CLOCK_BUS_APB1},
173 {.clock_id = NPCM_CLOCK_PECI, .bus = NPCM_CLOCK_BUS_FMCLK},
175 {.clock_id = NPCM_CLOCK_UART4, .bus = NPCM_CLOCK_BUS_APB2},
177 {.clock_id = NPCM_CLOCK_ESPI, .bus = NPCM_CLOCK_BUS_APB3},
179 {.clock_id = NPCM_CLOCK_SMB7, .bus = NPCM_CLOCK_BUS_APB3},
180 {.clock_id = NPCM_CLOCK_SMB8, .bus = NPCM_CLOCK_BUS_APB3},
181 {.clock_id = NPCM_CLOCK_SMB9, .bus = NPCM_CLOCK_BUS_APB3},
182 {.clock_id = NPCM_CLOCK_SMB10, .bus = NPCM_CLOCK_BUS_APB3},
183 {.clock_id = NPCM_CLOCK_SMB11, .bus = NPCM_CLOCK_BUS_APB3},
184 {.clock_id = NPCM_CLOCK_SMB12, .bus = NPCM_CLOCK_BUS_APB3},
187 /* PMC multi-registers */
188 #define NPCM_PWDWN_CTL_OFFSET(n) (((n) < 7) ? (0x07 + n) : (0x15 + (n - 7)))
193 #define DRV_CONFIG(dev) ((const struct npcm_pcc_config *)(dev)->config)
214 const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc; in npcm_clock_control_on()
219 return -EINVAL; in npcm_clock_control_on()
222 /* Clear related PD (Power-Down) bit of module to turn on clock */ in npcm_clock_control_on()
223 NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) &= in npcm_clock_control_on()
224 ~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id))); in npcm_clock_control_on()
233 const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc; in npcm_clock_control_off()
238 return -EINVAL; in npcm_clock_control_off()
241 /* Set related PD (Power-Down) bit of module to turn off clock */ in npcm_clock_control_off()
242 NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) |= in npcm_clock_control_off()
243 ~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id))); in npcm_clock_control_off()
257 return -EINVAL; in npcm_clock_control_get_subsys_rate()
260 switch (priv->bus) { in npcm_clock_control_get_subsys_rate()
297 return -EINVAL; in npcm_clock_control_get_subsys_rate()
312 struct cdcg_reg *const priv = (struct cdcg_reg *)(DRV_CONFIG(dev)->base_cdcg); in npcm_clock_control_init()
325 return -EINVAL; in npcm_clock_control_init()
333 if (priv->hfcgn != freq_p->hfcgn || priv->hfcgml != freq_p->hfcgml || in npcm_clock_control_init()
334 priv->hfcgmh != freq_p->hfcgmh) { in npcm_clock_control_init()
336 * Configure frequency multiplier M/N values according to in npcm_clock_control_init()
339 priv->hfcgn = freq_p->hfcgn; in npcm_clock_control_init()
340 priv->hfcgml = freq_p->hfcgml; in npcm_clock_control_init()
341 priv->hfcgmh = freq_p->hfcgmh; in npcm_clock_control_init()
343 /* Load M and N values into the frequency multiplier */ in npcm_clock_control_init()
344 priv->hfcgctrl |= BIT(NPCM_HFCGCTRL_LOAD); in npcm_clock_control_init()
346 while (sys_test_bit(priv->hfcgctrl, NPCM_HFCGCTRL_CLK_CHNG)) in npcm_clock_control_init()
351 priv->hfcgp = (FPRED_VAL << 4) | AHB6DIV_VAL; in npcm_clock_control_init()
352 priv->hfcbcd = APB1DIV_VAL | (APB2DIV_VAL << 4); in npcm_clock_control_init()
353 priv->hfcbcd1 = (I3CDIV_VAL << 2) | FIUDIV_VAL; in npcm_clock_control_init()
354 priv->hfcbcd2 = APB3DIV_VAL; in npcm_clock_control_init()