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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx-iomuxc.yaml5 This compatible binding should be applied to the device's iomuxc DTS node.
13 compatible: "nxp,imx-iomuxc"
40 Some IOMUXC options require writing to an IOMUXC_GPR register to select
54 RT11xx parts have multiple types of IOMUXC registers defined, with
61 RT11xx parts have multiple types of IOMUXC registers defined, with
68 RT11xx parts have multiple types of IOMUXC registers defined, with
75 RT11xx parts have multiple types of IOMUXC registers defined, with
Dnxp,imx-iomuxc-scu.yaml6 IOMUXC is managed by the SCU.
8 compatible: "nxp,imx-iomuxc-scu"
13 description: SCFW-based IOMUXC pin mux.
Dnxp,imx7d-pinctrl.yaml11 Note that the soc level iomuxc dts file can be examined to find the possible
13 IOMUXC SW_PAD_CTL register:
57 Pin mux selections for this group. See the soc level iomuxc DTSI file
68 Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
76 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
88 Select pull up resistor value. Sets PS field in IOMUXC peripheral.
Dnxp,mcux-rt-pinctrl.yaml23 Note that the soc level iomuxc dts file can be examined to find the possible
25 IOMUXC SW_PAD_CTL register:
74 Pin mux selections for this group. See the soc level iomuxc DTSI file
89 Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
111 Corresponds to the PUS field in the IOMUXC peripheral.
126 Corresponds to the PUS field in the IOMUXC peripheral. 100k is
136 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
147 Sets pin speed. Corresponds to SPEED field in IOMUXC peripheral
Dnxp,mcux-rt11xx-pinctrl.yaml22 Note that the soc level iomuxc dts file can be examined to find the possible
24 IOMUXC SW_PAD_CTL register:
71 Pin mux selections for this group. See the soc level iomuxc DTSI file
79 Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
88 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
Dnxp,imx8mp-pinctrl.yaml23 Note that the soc level iomuxc dts file can be examined to find the possible
25 IOMUXC SW_PAD_CTL register:
69 Pin mux selections for this group. See the soc level iomuxc DTSI file
80 Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
92 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
Dnxp,imx93-pinctrl.yaml23 Note that the soc level iomuxc dts file can be examined to find the possible
25 IOMUXC SW_PAD_CTL register:
69 Pin mux selections for this group. See the soc level iomuxc DTSI file
83 Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
100 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
Dnxp,imx8m-pinctrl.yaml22 Note that the soc level iomuxc dts file can be examined to find the possible
24 IOMUXC SW_PAD_CTL register:
68 Pin mux selections for this group. See the soc level iomuxc DTSI file
83 Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
104 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
112 Enable LVTTL input. Sets LVTTL field in IOMUXC peripheral
Dnxp,imx-gpr.yaml4 description: i.MX IOMUXC node
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dmmu_regions.c33 MMU_REGION_FLAT_ENTRY("IOMUXC",
34 DT_REG_ADDR(DT_NODELABEL(iomuxc)),
35 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
Dpinctrl_soc.h40 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
41 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
42 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx9/imx93/a55/
Dmmu_regions.c28 MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),
29 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dpinctrl_soc.h48 uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
49 uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
50 uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
51 uint32_t gpr_register; /* IOMUXC GPR register */
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dpinctrl_soc.h40 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
41 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
42 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx9/imx93/
Dpinctrl_soc.h38 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
39 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
40 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/
Dpinctrl_soc.h40 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
41 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
42 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dpinctrl_soc.h40 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
41 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
42 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/
Dpinctrl_soc.h39 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
40 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
41 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx9/imx95/
Dpinctrl_soc.h51 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
52 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
53 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx6sx/
Dpinctrl_soc.h51 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
52 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
53 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/soc/nxp/imx/imx7d/
Dpinctrl_soc.h52 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
53 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
54 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8m.dtsi116 iomuxc: iomuxc@30330000 { label
117 compatible = "nxp,imx-iomuxc";
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dpinctrl_soc.h94 uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
95 uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
96 uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
97 uint32_t gpr_register; /* IOMUXC GPR register */
/Zephyr-latest/modules/
DKconfig.imx31 Set if the IOMUXC module is present in the SoC.
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dpinctrl_soc.h74 uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
75 uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
76 uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */

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