Searched +full:cortex +full:- +full:m4 (Results 1 – 25 of 290) sorted by relevance
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| /Zephyr-latest/soc/infineon/cat1a/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
34 bool "Dual-core support [activate Cortex-M4]"
37 Cortex-M0 CPU should boot Cortex-M4
40 ## PSOC™ 6 Cortex M0+ prebuilt images
42 prompt "PSOC™ 6 Cortex M0+ prebuilt images"
44 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6
45 dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
50 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE
51 dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
52 application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
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| /Zephyr-latest/boards/st/stm32mp157c_dk2/doc/ |
| D | stm32mp157_dk2.rst | 6 The STM32MP157-DK2 Discovery board leverages the capacities of the STM32MP157
7 multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
8 Zephyr OS is ported to run on the Cortex®-M4 core.
10 - Common features:
12 - STM32MP157:
14 - Arm®-based dual Cortex®-A7 32 bits
15 - Cortex®-M4 32 bits
16 - embedded SRAM (448 Kbytes) for Cortex®-M4.
18 - ST PMIC STPMIC1A
19 - 4-Gbit DDR3L, 16 bits, 533 MHz
[all …]
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| /Zephyr-latest/boards/oct/osd32mp1_brk/doc/ |
| D | osd32mp1_brk.rst | 6 The OSD32MP1-BRK development board by Octavo Systems integrates the OSD32MP15x
7 System-in-Package (SiP), which contains a multicore STM32MP157F microprocessor.
8 Zephyr OS is ported to run on the Cortex®-M4 core of the STM32MP157F.
10 - Common features:
12 - OSD32MP15x SiP:
14 - STM32MP15x microprocessor:
15 - Dual-core Arm® Cortex®-A7 up to 800 MHz, 32 bits
16 - Cortex®-M4 up to 209 MHz, 32 bits
17 - Embedded SRAM (448 Kbytes) for Cortex®-M4.
19 - 512MB DDR3 memory
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| /Zephyr-latest/dts/bindings/cpu/ |
| D | arm,cortex-m4.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M4 CPU
6 compatible: "arm,cortex-m4"
8 include: arm,cortex-m.yaml
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| /Zephyr-latest/boards/96boards/avenger96/doc/ |
| D | index.rst | 10 multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
11 core. Zephyr OS is ported to run on the Cortex®-M4 core.
13 - Board features:
15 - PMIC: STPMIC1A
16 - RAM: 1024 Mbyte @ 533MHz
17 - Storage:
19 - eMMC: v4.51: 8 Gbyte
20 - QSPI: 2Mbyte
21 - EEPROM: 128 byte
22 - microSD Socket: UHS-1 v3.01
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| /Zephyr-latest/boards/udoo/udoo_neo_full/doc/ |
| D | index.rst | 8 composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4
9 core running up to 227 MHz for high CPU performance and real-time response.
10 Zephyr was ported to run on the Cortex-M4 core only. In a future release, it
11 will also communicate with the Cortex-A9 core (running Linux) via OpenAMP.
16 - MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core
18 - Memory
20 - 1 GB RAM
21 - 128 KB OCRAM
22 - 256 KB L2 cache (can be switched into OCRAM instead)
23 - 16 KB OCRAM_S
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| /Zephyr-latest/boards/gd/gd32f407v_start/doc/ |
| D | index.rst | 6 The GD32F407V-START board is a hardware platform that enables prototyping
7 on GD32F407VE Cortex-M4 High Performance MCU.
9 The GD32F407VE features a single-core ARM Cortex-M4 MCU which can run up
16 - GD32F407VET6 MCU
17 - 1 x User LEDs
18 - 1 x User Push buttons
19 - 1 x USART
20 - GD-Link on board programmer
21 - J-Link/SWD connector
23 For more information about the GD32F407 SoC and GD32F407V-START board:
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| /Zephyr-latest/boards/technexion/pico_pi/doc/ |
| D | index.rst | 6 The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7
7 core and Single Cortex M4 core.
8 Zephyr was ported to run on the M4 core. In a later release, it will also
14 The Pico-Pi Platform is composed of a CPU and IO board.
16 Pico-Pi IO Board
18 - S1 - On/Off (MX7_ONOFF signal)
19 - Board to board connector : Edison compatible connector (70 configurable pins)
20 - mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART)
21 - 10-pin needle JTAG Connector
22 - Debug USB exposing One UART
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| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | cypress,psoc6-intmux.yaml | 3 # SPDX-License-Identifier: Apache-2.0
8 The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
10 to be processed in the Cortex-M0+ CPU.
13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
21 configuration and how the Cortex-M0+ NVIC sources are organized. Each
22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
24 Cortex-M0+ NVIC controller line.
31 In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
33 the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
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| /Zephyr-latest/samples/bluetooth/hci_uart/dts/arm/nordic/ |
| D | override.dtsi | 2 * ARM Cortex-M4 lowest priority value of 5, i.e. considering Zephyr reserved 2
4 * ARM Cortex-M0 lowest priority value of 3, i.e. we use it as Zephyr has no
5 * support for ZLI on Cortex-M0.
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| /Zephyr-latest/boards/st/stm32h747i_disco/doc/ |
| D | index.rst | 7 from audio, multi-sensor support, graphics, security, video,
8 and high-speed connectivity features.
10 The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU,
12 large set of peripherals, SMPS, and MIPI-DSI.
16 - On-board ST-LINK/V3E supporting USB reenumeration capability
17 - USB ST-LINK functions: virtual COM port, mass storage, debug port
18 - Flexible power-supply options:
20 - ST-LINK USB VBUS, USB OTG HS connector, or external sources
22 - 4” capacitive touch LCD display module with MIPI® DSI interface
23 - Ethernet compliant with IEEE802.3-2002
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| /Zephyr-latest/boards/arduino/opta/doc/ |
| D | index.rst | 10 programming language and standard IEC-61131-3 PLC programming languages,
16 the M4 making the M7 run the PLC tasks while the M4 core under Zephyr acts as
21 - Ethernet compliant with IEEE802.3-2002
22 - 16MB QSPI Flash
23 - 4 x green color status LEDs
24 - 1 x green or red led over the reset push-button
25 - 1 x blue led over the user push-button (Opta Advanced only)
26 - 1 x user push-button
27 - 1 x reset push-button accessible via pinhole
28 - 8 x analog inputs
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| /Zephyr-latest/boards/st/stm32h745i_disco/doc/ |
| D | index.rst | 6 The STM32H745I-DISCO Discovery kit is a complete demonstration and development
7 platform for STMicroelectronics Arm |reg| Cortex |reg|‑M7 and Cortex |reg|‑M4 core-based STM32H745X…
12 Quad-SPI flash memory, and RGB interface LCD with capacitive multi-touch panel). ARDUINO |reg| Uno …
15 STLINK-V3E is integrated into the board, as an embedded in-circuit debugger and programmer for the
20 - Arm |reg| Cortex |reg| core-based microcontroller with 2 Mbytes of flash memory and 1 Mbyte of RA…
21 - 4.3” RGB interface LCD with touch panel connector
22 - Ethernet compliant with IEEE-802.3-2002, and PoE
23 - USB OTG FS
24 - SAI audio codec
25 - One ST-MEMS digital microphone
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| /Zephyr-latest/boards/96boards/meerkat96/doc/ |
| D | index.rst | 9 96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor,
10 composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
11 Zephyr OS is ported to run on the Cortex®-M4 core.
13 - Board features:
15 - RAM: 512 Mbyte
16 - Storage:
18 - microSD Socket
19 - Wireless:
21 - WiFi: 2.4GHz IEEE 802.11b/g/n
22 - Bluetooth: v4.1 (BR/EDR)
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| /Zephyr-latest/boards/element14/warp7/doc/ |
| D | index.rst | 6 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
7 core and Single Cortex M4 core.
8 Zephyr was ported to run on the M4 core. In a later release, it will also
19 - 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface)
20 - 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface)
21 - Altimeter: NXP MPL3115A2 (I2C4 interface)
22 - NXP NTAG NT3H1101 (I2C2 interface)
23 - Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces)
24 - S1 - Reset Button (POR_B signal)
25 - S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal)
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| /Zephyr-latest/boards/toradex/colibri_imx7d/doc/ |
| D | index.rst | 6 The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7
7 core and Single Cortex M4 core.
8 Zephyr was ported to run on the M4 core. In a later release, it will also
14 - i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
16 - Memory
18 - RAM -> A7: 256MB, 512MB and 1GB
19 - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
20 - Flash -> A7: 4Gb eMMC and 512Mb NAND
22 - Display
24 - RGB 1920x1080x24bpp
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| /Zephyr-latest/boards/nxp/imx8mm_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
8 Zephyr OS is ported to run on the Cortex®-A53 core.
10 - Board features:
12 - RAM: 2GB LPDDR4
13 - Storage:
15 - SanDisk 16GB eMMC5.1
16 - Micron 32MB QSPI NOR
17 - microSD Socket
18 - Wireless:
20 - WiFi: 2.4/5GHz IEEE 802.11b/g/n
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| /Zephyr-latest/boards/toradex/verdin_imx8mm/doc/ |
| D | index.rst | 9 8M Mini SoloLite. The top-tier i.MX 8M Mini Quad features four Cortex-A53 cores as the main
10 processor cluster. The cores provide complete 64-bit Armv8-A support while maintaining seamless
11 backwards compatibility with 32-bit Armv7-A software. The main cores run at up to 1.8 GHz for
14 In addition to the main CPU complex, the i.MX 8M Mini features a Cortex-M4F processor which
17 multicore system allows for the running of additional real-time operating systems on the M4 cores
18 for time- and security-critical tasks.
20 - Board features:
22 - RAM: 1GB - 2GB (LPDDR4)
23 - Storage:
25 - 4GB - 17GB eMMC
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| /Zephyr-latest/soc/arm/mps2/ |
| D | Kconfig.soc | 1 # Copyright (c) 2017-2019 Linaro Limited
2 # Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 # SPDX-License-Identifier: Apache-2.0
15 ARM Cortex-M0+ SMM on V2M-MPS2 (Application Note AN383)
21 ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)
27 ARM Cortex-M4 SMM on V2M-MPS2 (Application Note AN386)
33 ARM Cortex-M7 SMM on V2M-MPS2+ (Application Note AN500)
43 ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0
49 ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1
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| /Zephyr-latest/boards/st/nucleo_h755zi_q/doc/ |
| D | index.rst | 6 The NUCLEO-H755ZI-Q board, based on the MB1363 reference board, provides an affordable and
13 The NUCLEO-H755ZI-Q board does not require any separate probe as it integrates
14 the ST-LINK V3 debugger/programmer.
18 - STM32H755ZIT6 microcontroller in LQFP144 package
19 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
20 - USB OTG or full-speed device (depending on STM32 support)
21 - 3 user LEDs
22 - 2 user and reset push-buttons
23 - 32.768 kHz crystal oscillator
24 - Board connectors:
[all …]
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| /Zephyr-latest/boards/nxp/imx8mq_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
8 Zephyr OS is ported to run on the Cortex®-M4 core.
10 - Board features:
12 - RAM: 3GB LPDDR4
13 - Storage:
15 - 16GB eMMC5.0
16 - 32MB QSPI NOR
17 - microSD Socket
18 - Wireless:
20 - WiFi: 2.4/5GHz IEEE 802.11 a/b/g/n/ac
[all …]
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| /Zephyr-latest/boards/arduino/nicla_vision/doc/ |
| D | index.rst | 7 STM32H747GAII, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash
12 - RGB LED
13 - Reset Boot button
14 - USB device
15 - Murata Type 1DX Bluetooth + WiFi module (CYW4343W based)
16 - GC2145 2 Megapixel Camera Sensor
17 - SE050C2HQ1 Crypto IC
18 - MP34DT06JTR Omnidirectional Microphone
19 - VL53L1CBV0FY ToF Sensor
20 - LSM6DSOXTR Gyro+Accelerometer Sensor
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| /Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/ |
| D | soc.c | 2 * Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
20 /* Move M4 core to specific RDC domain 1 */ in SOC_RdcInit()
27 * The M4 core is running at domain 1, enable clock gate for in SOC_RdcInit()
37 * The M4 core is running at domain 1, enable the PLL clock sources in SOC_RdcInit()
61 * Switch AXI M4 root to 25M first in order to configure in SOC_ClockInit()
66 /* Switch cortex-m4 to SYSTEM PLL1 DIV3 */ in SOC_ClockInit()
101 * sure the M4 core could work normally when A53 core in SOC_ClockInit()
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| /Zephyr-latest/boards/st/nucleo_h745zi_q/doc/ |
| D | index.rst | 6 The STM32 Nucleo-144 board provides an affordable and flexible way for users
15 The STM32 Nucleo-144 board does not require any separate probe as it integrates
16 the ST-LINK V3 debugger/programmer.
18 The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
23 - STM32 microcontroller in LQFP144 package
24 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
25 - USB OTG or full-speed device (depending on STM32 support)
26 - 3 user LEDs
27 - 2 user and reset push-buttons
28 - 32.768 kHz crystal oscillator
[all …]
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| /Zephyr-latest/samples/drivers/ipm/ipm_mcux/ |
| D | README.rst | 1 .. zephyr:code-sample:: ipm-mcux
3 :relevant-api: ipm_interface
5 Implement inter-processor mailbox (IPM) on NXP LPC family.
10 Some NXP microcontrollers from LPC family are dual-core, this
15 - :zephyr:board:`lpcxpresso54114`, two core processors (Cortex-M4F and Cortex-M0+)
16 - :zephyr:board:`lpcxpresso55s69`, two core processors (dual Cortex-M33)
21 - :zephyr:board:`lpcxpresso54114` board
22 - :zephyr:board:`lpcxpresso55s69` board
24 Building the application for lpcxpresso54114/lpc54114/m4
27 .. zephyr-app-commands::
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