1.. zephyr:board:: warp7
2
3Overview
4********
5
6The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
7core and Single Cortex M4 core.
8Zephyr was ported to run on the M4 core. In a later release, it will also
9communicate with the A7 core (running Linux) via RPmsg.
10
11Hardware
12********
13
14The WaRP7 Platform is composed of a CPU and IO board.
15
16WaRP7 IO Board
17==============
18
19- 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface)
20- 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface)
21- Altimeter: NXP MPL3115A2 (I2C4 interface)
22- NXP NTAG NT3H1101 (I2C2 interface)
23- Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces)
24- S1 - Reset Button (POR_B signal)
25- S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal)
26- S3 - On/Off (MX7_ONOFF signal)
27- Board to board connector (34 configurable pins)
28- mikroBUS expansion connector
29- 10-pin needle JTAG Connector
30- Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4)
31- MIPI DSI 1 lane Connector
32- LCD Touch Connector (I2C2 interface)
33- Audio Jack: Mic and Stereo Headphone
34
35WaRP7 CPU Board
36===============
37
38- CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and
39  Single Cortex M4 (200MHz) core
40- Memory
41
42  - RAM -> A7: 4GB (Kingston 08EMCP04)
43  - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
44  - Flash -> A7: 8GB eMMC (Kingston 08EMCP04)
45- Multimedia
46
47  - MIPI CSI 1 lane connector with 5MP OV5640 camera module (I2C2 interface)
48- Connectivity
49
50  - Board to board connector (34 configurable pins)
51  - Micro USB 2.0 OTG connector (USB_OTG1 interface)
52  - Murata Type 1DX Wi-Fi IEEE 802.11b/g/n and Bluetooth 4.1 plus EDR
53    (SD1, UART3 SAI2 interfaces)
54- Li-ion/Li-polymer Battery Charger: NXP BC3770 (I2C1 interface)
55- Power management integrated circuit (PMIC): NXP PF3000 (I2C1 interface)
56
57
58For more information about the i.MX7 SoC and WaRP7, see these references:
59
60- `i.MX 7 Series Website`_
61- `i.MX 7 Solo Datasheet`_
62- `i.MX 7 Solo Reference Manual`_
63- `WaRP7 Site`_
64- `WaRP7 Quick Start Guide`_
65- `WaRP7 User Guide`_
66- `WaRP7 GitHub repository`_
67
68Supported Features
69==================
70
71The WaRP7 configuration supports the following hardware features on the
72Cortex M4 Core:
73
74+-----------+------------+-------------------------------------+
75| Interface | Controller | Driver/Component                    |
76+===========+============+=====================================+
77| NVIC      | on-chip    | nested vector interrupt controller  |
78+-----------+------------+-------------------------------------+
79| SYSTICK   | on-chip    | systick                             |
80+-----------+------------+-------------------------------------+
81| GPIO      | on-chip    | gpio                                |
82+-----------+------------+-------------------------------------+
83| I2C       | on-chip    | i2c                                 |
84+-----------+------------+-------------------------------------+
85| UART      | on-chip    | serial port-polling;                |
86|           |            | serial port-interrupt               |
87+-----------+------------+-------------------------------------+
88| SENSOR    | off-chip   | fxos8700 polling;                   |
89|           |            | fxos8700 trigger;                   |
90|           |            | fxas21002 polling;                  |
91|           |            | fxas21002 trigger;                  |
92+-----------+------------+-------------------------------------+
93
94The default configuration can be found in the defconfig file:
95:zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4_defconfig`
96
97Other hardware features are not currently supported by the port.
98
99Connections and IOs
100===================
101
102The WaRP7 board Board was tested with the following pinmux controller
103configuration.
104
105+---------------+---------------------+--------------------------------+
106| Board Name    | SoC Name            | Usage                          |
107+===============+=====================+================================+
108| FT_TX2        | UART2_TXD           | UART Console                   |
109+---------------+---------------------+--------------------------------+
110| FT_RX2        | UART2_RXD           | UART Console                   |
111+---------------+---------------------+--------------------------------+
112| MKBUS_TX      | UART6_TXD           | UART                           |
113+---------------+---------------------+--------------------------------+
114| MKBUS_RX      | UART6_RXD           | UART                           |
115+---------------+---------------------+--------------------------------+
116| S2            | ENET1_RD1/GPIO7_IO1 | SW0                            |
117+---------------+---------------------+--------------------------------+
118| I2C4_SDA      | I2C4_SDA            | I2C / FXOS8700 / FXAS21002     |
119+---------------+---------------------+--------------------------------+
120| I2C4_SCL      | I2C4_SCL            | I2C / FXOS8700 / FXAS21002     |
121+---------------+---------------------+--------------------------------+
122| SENSOR_INT_B  | ENET1_RD0/GPIO7_IO0 | FXOS8700 INT1 / FXAS21002 INT1 |
123+---------------+---------------------+--------------------------------+
124
125System Clock
126============
127
128The M4 Core is configured to run at a 200 MHz clock speed.
129
130Serial Port
131===========
132
133The iMX7S SoC has seven UARTs. The number 2 is configured for the console and
134the number 6 is used in the mikroBUS connector.
135
136Programming and Debugging
137*************************
138
139The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by
140the A7 core. The A7 core is responsible to load the M4 binary application into
141the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and
142get the M4 out of reset.
143The A7 can perform these steps at bootloader level or after the Linux system
144has booted.
145
146The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and
147M4:
148
149+------------+-----------------------+------------------------+-----------------------+----------------------+
150| Region     | Cortex-A7             | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus)  | Size                 |
151+============+=======================+========================+=======================+======================+
152| DDR        | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF  | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) |
153+------------+-----------------------+------------------------+-----------------------+----------------------+
154| OCRAM      | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF  | 0x00900000-0x0091FFFF | 128KB                |
155+------------+-----------------------+------------------------+-----------------------+----------------------+
156| TCMU       | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF  |                       | 32KB                 |
157+------------+-----------------------+------------------------+-----------------------+----------------------+
158| TCML       | 0x007F8000-0x007FFFFF |                        | 0x1FFF8000-0x1FFFFFFF | 32KB                 |
159+------------+-----------------------+------------------------+-----------------------+----------------------+
160| OCRAM_S    | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF  | 0x00000000-0x00007FFF | 32KB                 |
161+------------+-----------------------+------------------------+-----------------------+----------------------+
162| QSPI Flash |                       |                        | 0x08000000-0x0BFFFFFF | 64MB                 |
163+------------+-----------------------+------------------------+-----------------------+----------------------+
164
165
166References
167==========
168
169- `i.MX 7 Solo Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3)
170- `Toradex Wiki`_
171
172
173At compilation time you have to choose which RAM will be used. This
174configuration is done in the file :zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4.dts` with
175"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available
176configurations are:
177
178.. code-block:: none
179
180   "zephyr,flash"
181   - &ddr_code
182   - &tcml_code
183   - &ocram_code
184   - &ocram_s_code
185   - &ocram_pxp_code
186   - &ocram_epdc_code
187
188   "zephyr,sram"
189   - &ddr_sys
190   - &tcmu_sys
191   - &ocram_sys
192   - &ocram_s_sys
193   - &ocram_pxp_sys
194   - &ocram_epdc_sys
195
196
197Below you will find the instructions to load and run Zephyr on M4 from A7 using
198u-boot.
199
200Connect both micro USB interfaces into the PC. In one USB interface you will
201have 2 USB serial ports, the first one is the A7 console and the second is the
202M4 console for Zephyr with both configured to work at 115200 8N1.
203The other USB interface is used to power the CPU and IO boards and is connected
204to the USB OTG interface of the i.MX7S.
205
206After powering up the platform stop the u-boot execution on the A7 core and
207expose the eMMC as mass storage with the following command in the u-boot
208prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT
209partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the
210u-boot prompt.
211Set the u-boot environment variables and run the zephyr.bin from the
212appropriated memory configured in the Zephyr compilation:
213
214.. code-block:: console
215
216   setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr'
217   # TCML
218   setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000'
219   setenv bootm4tcml 'run m4tcml && run bootm4'
220   run bootm4tcml
221   # TCMU
222   setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000'
223   setenv bootm4tcmu 'run m4tcmu && run bootm4'
224   run bootm4tcmu
225   # OCRAM
226   setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000'
227   setenv bootm4ocram 'run m4ocram && run bootm4'
228   run bootm4ocram
229   # OCRAM_S
230   setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000'
231   setenv bootm4ocrams 'run m4ocrams && run bootm4'
232   run bootm4ocrams
233   # DDR
234   setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000'
235   setenv bootm4ddr 'run m4ddr && run bootm4'
236   run bootm4ddr
237
238
239Debugging
240=========
241
242Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_.
243
244To run Zephyr Binary using J-Link, create the following script to get the
245Program Counter and Stack Pointer from ``zephyr.bin``.
246
247get-pc-sp.sh:
248.. code-block:: console
249
250   #!/bin/sh
251
252   firmware=$1
253
254   pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}')
255   sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}')
256
257   echo pc=$pc
258   echo sp=$sp
259
260
261Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin``
262.. code-block:: console
263
264   pc=00900f01
265   sp=00905020
266
267Plug in the J-Link into the board and PC and run the J-Link command line tool:
268
269.. code-block:: console
270
271   /usr/bin/JLinkExe -device Cortex-M4 -if JTAG \
272      -speed 4000 -autoconnect 1 -jtagconf -1,-1 \
273      -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript
274
275The following steps are necessary to run the zephyr.bin:
276
2771. Put the M4 core in reset
2782. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR)
2793. Set PC (Program Counter)
2804. Set SP (Stack Pointer)
2815. Get the M4 core out of reset
282
283Issue the following commands inside J-Link commander:
284
285.. code-block:: console
286
287   w4 0x3039000C 0xAC
288   loadfile zephyr.bin,0x00900000
289   w4 0x00180000 00900f01
290   w4 0x00180004 00905020
291   w4 0x3039000C 0xAA
292
293With these mechanisms, applications for the ``warp7`` board
294configuration can be built and debugged in the usual way (see
295:ref:`build_an_application` and :ref:`application_run` for more details).
296
297References
298==========
299
300- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_
301- `J-Link iMX7D Instructions`_
302
303.. _WaRP7 Site:
304   https://www.element14.com/warp7
305
306.. _WaRP7 User Guide:
307   https://github.com/WaRP7/WaRP7-User-Guide/releases/download/v1.3/User_Guide_Manual_v1-3.pdf
308
309.. _WaRP7 Quick Start Guide:
310   https://www.nxp.com/docs/en/supporting-information/WARP7-LEAFLET-QSG.pdf
311
312.. _WaRP7 GitHub repository:
313   https://github.com/WaRP7
314
315.. _i.MX 7 Series Website:
316   https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1
317
318.. _i.MX 7 Solo Datasheet:
319   https://www.nxp.com/docs/en/data-sheet/IMX7SCEC.pdf
320
321.. _i.MX 7 Solo Reference Manual:
322   https://www.nxp.com/webapp/Download?colCode=IMX7SRM
323
324.. _J-Link Tools:
325   https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack
326
327.. _NXP iMX7D Connect CortexM4.JLinkScript:
328   https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript
329
330.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors:
331   https://www.nxp.com/docs/en/application-note/AN5317.pdf
332
333.. _J-Link iMX7D Instructions:
334   https://wiki.segger.com/IMX7D
335
336.. _Toradex Wiki:
337   https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas
338