1.. zephyr:board:: stm32h747i_disco
2
3Overview
4********
5
6The discovery kit enables a wide diversity of applications taking benefit
7from audio, multi-sensor support, graphics, security, video,
8and high-speed connectivity features.
9
10The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU,
11with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface,
12large set of peripherals, SMPS, and MIPI-DSI.
13
14Additionally, the board features:
15
16- On-board ST-LINK/V3E supporting USB reenumeration capability
17- USB ST-LINK functions: virtual COM port, mass storage, debug port
18- Flexible power-supply options:
19
20  - ST-LINK USB VBUS, USB OTG HS connector, or external sources
21
22- 4” capacitive touch LCD display module with MIPI® DSI interface
23- Ethernet compliant with IEEE802.3-2002
24- USB OTG HS
25- Stereo speaker outputs
26- ST-MEMS digital microphones
27- 2 x 512-Mbit QUAD-SPI NOR Flash memory
28- 256-Mbit SDRAM
29- 4 color user LEDs
30- 1 user and reset push-button
31- 4-direction joystick with selection button
32- Arduino Uno V3 connectors
33
34More information about the board can be found at the `STM32H747I-DISCO website`_.
35More information about STM32H747XIH6 can be found here:
36
37- `STM32H747XI on www.st.com`_
38- `STM32H747xx reference manual`_
39- `STM32H747xx datasheet`_
40
41Supported Features
42==================
43
44The current Zephyr stm32h747i_disco board configuration supports the following hardware features:
45
46+-----------+------------+-------------------------------------+
47| Interface | Controller | Driver/Component                    |
48+===========+============+=====================================+
49| NVIC      | on-chip    | nested vector interrupt controller  |
50+-----------+------------+-------------------------------------+
51| UART      | on-chip    | serial port-polling;                |
52|           |            | serial port-interrupt               |
53+-----------+------------+-------------------------------------+
54| PINMUX    | on-chip    | pinmux                              |
55+-----------+------------+-------------------------------------+
56| GPIO      | on-chip    | gpio                                |
57+-----------+------------+-------------------------------------+
58| FLASH     | on-chip    | flash memory                        |
59+-----------+------------+-------------------------------------+
60| ETHERNET  | on-chip    | ethernet  (*)                       |
61+-----------+------------+-------------------------------------+
62| RNG       | on-chip    | True Random number generator        |
63+-----------+------------+-------------------------------------+
64| FMC       | on-chip    | memc (SDRAM)                        |
65+-----------+------------+-------------------------------------+
66| SPI       | on-chip    | spi                                 |
67+-----------+------------+-------------------------------------+
68| QSPI NOR  | on-chip    | off-chip flash                      |
69+-----------+------------+-------------------------------------+
70| SDMMC     | on-chip    | disk access                         |
71+-----------+------------+-------------------------------------+
72| IPM       | on-chip    | virtual mailbox based on HSEM       |
73+-----------+------------+-------------------------------------+
74| DISPLAY   | on-chip    | MIPI DSI Host with shield (MP1166)  |
75|           |            | st_b_lcd40_dsi1_mb1166              |
76+-----------+------------+-------------------------------------+
77
78(*) From UM2411 Rev 4:
79   With the default setting, the Ethernet feature is not working because of
80   a conflict between ETH_MDC and SAI4_D1 of the MEMs digital microphone.
81   Make sure you have SB8 closed and SB21 open to get Ethernet working.
82
83Other hardware features are not yet supported on Zephyr porting.
84
85The default configuration per core can be found in the defconfig files:
86:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig` and
87:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig`
88
89Pin Mapping
90===========
91
92STM32H747I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing,
93input/output, pull-up, etc.
94
95For more details please refer to `STM32H747I-DISCO website`_.
96
97Default Zephyr Peripheral Mapping:
98----------------------------------
99
100- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com)
101- UART_8 TX/RX : PJ8/PJ9 (Arduino Serial)
102- SPI_5 NSS/SCK/MISO/MOSI : PK1/PK0/PJ11/PJ10 (Arduino SPI)
103- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2
104- LD1 : PI12
105- LD2 : PI13
106- LD3 : PI14
107- LD4 : PI15
108- W-UP : PC13
109- J-CENTER : PK2
110- J-DOWN : PK3
111- J-LEFT : PK4
112- J-RIGHT : PK5
113- J-UP : PK6
114
115System Clock
116============
117
118The STM32H747I System Clock can be driven by an internal or external oscillator,
119as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock
120is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock
121is driven at 200MHz. PLL clock is feed by a 25MHz high speed external clock.
122
123Serial Port
124===========
125
126The STM32H747I Discovery kit has up to 8 UARTs.
127Default configuration assigns USART1 and UART8 to the CPU1. The Zephyr console
128output is assigned to UART1 which connected to the onboard ST-LINK/V3.0. Virtual
129COM port interface. Default communication settings are 115200 8N1.
130
131Ethernet
132========
133
134**Disclaimer:** This section is mostly copy-paste of corresponding
135`DISCO_H747I modifications for Ethernet`_ mbed blog post. The author of this
136article sincerely allowed to use the images and his knowledge about necessary
137HW modifications to get Ethernet working with this board.
138
139To get Ethernet working following HW modifications are required:
140
141- **SB21**, **SB45** and **R87** should be opened
142- **SB22**, **SB44**, **SB17** and **SB8** should be closed
143
144Following two images shows necessary changes on the board marked:
145
146.. image:: img/disco_h747i_ethernet_modification_1.jpg
147     :align: center
148     :alt: STM32H747I-DISCO - Ethernet modification 1 (**SB44**, **SB45**)
149
150.. image:: img/disco_h747i_ethernet_modification_2.jpg
151     :align: center
152     :alt: STM32H747I-DISCO - Ethernet modification 2 (**SB21**, **R87**, **SB22**, **SB17** and **SB8**)
153
154Display
155=======
156
157The STM32H747I Discovery kit has a dedicated DSI LCD connector **CN15**, where
158the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display
159support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` or
160``st_b_lcd40_dsi1_mb1166_a09`` to your build command, for example:
161
162.. zephyr-app-commands::
163   :zephyr-app: samples/drivers/display
164   :board: stm32h747i_disco/stm32h747xx/m7
165   :shield: st_b_lcd40_dsi1_mb1166
166   :goals: build flash
167
168.. note::
169   The shield comes in different hardware revisions, the MB1166-A09
170   is utilizing a NT35510 panel controller and shall specifically
171   use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building.
172   Prior versions are utilizing an OTM8009a controller and shall
173   use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166``.
174   Shield version is printed on a sticker placed below the two bottom
175   mounting holes and has the format: MB1166-Axx.
176
177Resources sharing
178=================
179
180The dual core nature of STM32H747 SoC requires sharing HW resources between the
181two cores. This is done in 3 ways:
182
183- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
184  has access to bus clock activation and deactivation.
185- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in
186  devicetree before compilation. The user must ensure peripherals are not assigned
187  to both cores at the same time.
188- **Run time protection**: Interrupt-controller and GPIO configurations could be
189  accessed by both cores at run time. Accesses are protected by a hardware semaphore
190  to avoid potential concurrent access issues.
191
192Programming and Debugging
193*************************
194
195STM32H747I-DISCO board includes an ST-LINK/V3 embedded debug tool interface.
196
197Applications for the ``stm32h747i_disco`` board should be built per core target,
198using either ``stm32h747i_disco/stm32h747xx/m7`` or ``stm32h747i_disco/stm32h747xx/m4``
199as the target.
200See :ref:`build_an_application` for more information about application builds.
201
202.. note::
203
204   Check if the board's ST-LINK V3 has the newest FW version. It can be updated
205   using `STM32CubeProgrammer`_.
206
207.. note::
208
209   With OpenOCD, sometimes, flashing does not work. It is necessary to
210   erase the flash (with STM32CubeProgrammer for example) to make it work again.
211   Debugging with OpenOCD is currently working for this board only with Cortex M7,
212   not Cortex M4.
213
214
215Flashing
216========
217
218Flashing operation will depend on the target to be flashed and the SoC
219option bytes configuration.
220
221The board is configured to be flashed using west `STM32CubeProgrammer`_ runner
222for both cores, so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
223The target core is detected automatically.
224
225Alternatively, OpenOCD or JLink can also be used to flash the board using
226the ``--runner`` (or ``-r``) option:
227
228.. code-block:: console
229
230   $ west flash --runner openocd
231   $ west flash --runner jlink
232
233It is advised to use `STM32CubeProgrammer`_ to check and update option bytes
234configuration.
235
236By default:
237
238  - CPU1 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0)
239  - CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0)
240
241Also, default out of the box board configuration enables CM7 and CM4 boot when
242board is powered (Option bytes BCM7 and BCM4 are checked).
243It is possible to change Option Bytes so that CM7 boots first in stand alone,
244and CM7 will wakeup CM4 after clock initialization.
245Drivers are able to take into account both Option Bytes configurations
246automatically.
247
248Zephyr flash configuration has been set to meet these default settings.
249
250Flashing an application to STM32H747I M7 Core
251---------------------------------------------
252
253First, connect the STM32H747I Discovery kit to your host computer using
254the USB port to prepare it for flashing. Then build and flash your application.
255
256Here is an example for the :zephyr:code-sample:`hello_world` application.
257
258.. zephyr-app-commands::
259   :zephyr-app: samples/hello_world
260   :board: stm32h747i_disco/stm32h747xx/m7
261   :goals: build flash
262
263Run a serial host program to connect with your board:
264
265.. code-block:: console
266
267   $ minicom -D /dev/ttyACM0
268
269You should see the following message on the console:
270
271.. code-block:: console
272
273   Hello World! stm32h747i_disco
274
275.. note::
276  Sometimes, flashing is not working. It is necessary to erase the flash
277  (with STM32CubeProgrammer for example) to make it work again.
278
279Similarly, you can build and flash samples on the M4 target. For this, please
280take care of the resource sharing (UART port used for console for instance).
281
282Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
283
284.. zephyr-app-commands::
285   :zephyr-app: samples/basic/blinky
286   :board: stm32h747i_disco/stm32h747xx/m7
287   :goals: build flash
288
289Debugging
290=========
291
292You can debug an application on Cortex M7 side in the usual way.  Here is an example
293for the :zephyr:code-sample:`hello_world` application.
294
295.. zephyr-app-commands::
296   :zephyr-app: samples/hello_world
297   :board: stm32h747i_disco/stm32h747xx/m7
298   :goals: debug
299
300Debugging a Zephyr application on Cortex M4 side with west is currently not available.
301As a workaround, you can use `STM32CubeIDE`_.
302
303.. _STM32H747I-DISCO website:
304   https://www.st.com/en/evaluation-tools/stm32h747i-disco.html
305
306.. _STM32H747XI on www.st.com:
307   https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html
308
309.. _STM32H747xx reference manual:
310   https://www.st.com/resource/en/reference_manual/dm00176879.pdf
311
312.. _STM32H747xx datasheet:
313   https://www.st.com/resource/en/datasheet/stm32h747xi.pdf
314
315.. _STM32CubeProgrammer:
316   https://www.st.com/en/development-tools/stm32cubeprog.html
317
318.. _DISCO_H747I modifications for Ethernet:
319   https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet
320
321.. _STM32CubeIDE:
322   https://www.st.com/en/development-tools/stm32cubeide.html
323