Lines Matching +full:cortex +full:- +full:m4
6 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
7 core and Single Cortex M4 core.
8 Zephyr was ported to run on the M4 core. In a later release, it will also
19 - 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface)
20 - 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface)
21 - Altimeter: NXP MPL3115A2 (I2C4 interface)
22 - NXP NTAG NT3H1101 (I2C2 interface)
23 - Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces)
24 - S1 - Reset Button (POR_B signal)
25 - S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal)
26 - S3 - On/Off (MX7_ONOFF signal)
27 - Board to board connector (34 configurable pins)
28 - mikroBUS expansion connector
29 - 10-pin needle JTAG Connector
30 - Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4)
31 - MIPI DSI 1 lane Connector
32 - LCD Touch Connector (I2C2 interface)
33 - Audio Jack: Mic and Stereo Headphone
38 - CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and
39 Single Cortex M4 (200MHz) core
40 - Memory
42 - RAM -> A7: 4GB (Kingston 08EMCP04)
43 - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
44 - Flash -> A7: 8GB eMMC (Kingston 08EMCP04)
45 - Multimedia
47 - MIPI CSI 1 lane connector with 5MP OV5640 camera module (I2C2 interface)
48 - Connectivity
50 - Board to board connector (34 configurable pins)
51 - Micro USB 2.0 OTG connector (USB_OTG1 interface)
52 - Murata Type 1DX Wi-Fi IEEE 802.11b/g/n and Bluetooth 4.1 plus EDR
54 - Li-ion/Li-polymer Battery Charger: NXP BC3770 (I2C1 interface)
55 - Power management integrated circuit (PMIC): NXP PF3000 (I2C1 interface)
60 - `i.MX 7 Series Website`_
61 - `i.MX 7 Solo Datasheet`_
62 - `i.MX 7 Solo Reference Manual`_
63 - `WaRP7 Site`_
64 - `WaRP7 Quick Start Guide`_
65 - `WaRP7 User Guide`_
66 - `WaRP7 GitHub repository`_
72 Cortex M4 Core:
74 +-----------+------------+-------------------------------------+
77 | NVIC | on-chip | nested vector interrupt controller |
78 +-----------+------------+-------------------------------------+
79 | SYSTICK | on-chip | systick |
80 +-----------+------------+-------------------------------------+
81 | GPIO | on-chip | gpio |
82 +-----------+------------+-------------------------------------+
83 | I2C | on-chip | i2c |
84 +-----------+------------+-------------------------------------+
85 | UART | on-chip | serial port-polling; |
86 | | | serial port-interrupt |
87 +-----------+------------+-------------------------------------+
88 | SENSOR | off-chip | fxos8700 polling; |
92 +-----------+------------+-------------------------------------+
105 +---------------+---------------------+--------------------------------+
109 +---------------+---------------------+--------------------------------+
111 +---------------+---------------------+--------------------------------+
113 +---------------+---------------------+--------------------------------+
115 +---------------+---------------------+--------------------------------+
117 +---------------+---------------------+--------------------------------+
119 +---------------+---------------------+--------------------------------+
121 +---------------+---------------------+--------------------------------+
123 +---------------+---------------------+--------------------------------+
128 The M4 Core is configured to run at a 200 MHz clock speed.
139 The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by
140 the A7 core. The A7 core is responsible to load the M4 binary application into
141 the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and
142 get the M4 out of reset.
146 The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and
147 M4:
149 +------------+-----------------------+------------------------+-----------------------+------------…
150 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
152 | DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (les…
153 +------------+-----------------------+------------------------+-----------------------+------------…
154 | OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB …
155 +------------+-----------------------+------------------------+-----------------------+------------…
156 | TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB …
157 +------------+-----------------------+------------------------+-----------------------+------------…
158 | TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB …
159 +------------+-----------------------+------------------------+-----------------------+------------…
160 | OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB …
161 +------------+-----------------------+------------------------+-----------------------+------------…
162 | QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB …
163 +------------+-----------------------+------------------------+-----------------------+------------…
169 - `i.MX 7 Solo Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3)
170 - `Toradex Wiki`_
178 .. code-block:: none
181 - &ddr_code
182 - &tcml_code
183 - &ocram_code
184 - &ocram_s_code
185 - &ocram_pxp_code
186 - &ocram_epdc_code
189 - &ddr_sys
190 - &tcmu_sys
191 - &ocram_sys
192 - &ocram_s_sys
193 - &ocram_pxp_sys
194 - &ocram_epdc_sys
197 Below you will find the instructions to load and run Zephyr on M4 from A7 using
198 u-boot.
202 M4 console for Zephyr with both configured to work at 115200 8N1.
206 After powering up the platform stop the u-boot execution on the A7 core and
207 expose the eMMC as mass storage with the following command in the u-boot
210 u-boot prompt.
211 Set the u-boot environment variables and run the zephyr.bin from the
214 .. code-block:: console
242 Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_.
244 To run Zephyr Binary using J-Link, create the following script to get the
247 get-pc-sp.sh:
248 .. code-block:: console
254 pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}')
255 sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}')
261 Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin``
262 .. code-block:: console
267 Plug in the J-Link into the board and PC and run the J-Link command line tool:
269 .. code-block:: console
271 /usr/bin/JLinkExe -device Cortex-M4 -if JTAG \
272 -speed 4000 -autoconnect 1 -jtagconf -1,-1 \
273 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript
277 1. Put the M4 core in reset
281 5. Get the M4 core out of reset
283 Issue the following commands inside J-Link commander:
285 .. code-block:: console
300 - `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Proces…
301 - `J-Link iMX7D Instructions`_
307 https://github.com/WaRP7/WaRP7-User-Guide/releases/download/v1.3/User_Guide_Manual_v1-3.pdf
310 https://www.nxp.com/docs/en/supporting-information/WARP7-LEAFLET-QSG.pdf
316 …nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-process…
319 https://www.nxp.com/docs/en/data-sheet/IMX7SCEC.pdf
324 .. _J-Link Tools:
325 https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack
330 .. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Proce…
331 https://www.nxp.com/docs/en/application-note/AN5317.pdf
333 .. _J-Link iMX7D Instructions:
337 …https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_ar…