1.. zephyr:board:: stm32mp157c_dk2
2
3Overview
4********
5
6The STM32MP157-DK2 Discovery board leverages the capacities of the STM32MP157
7multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
8Zephyr OS is ported to run on the Cortex®-M4 core.
9
10- Common features:
11
12  - STM32MP157:
13
14    - Arm®-based dual Cortex®-A7 32 bits
15    - Cortex®-M4 32 bits
16    - embedded SRAM (448 Kbytes) for Cortex®-M4.
17
18  - ST PMIC STPMIC1A
19  - 4-Gbit DDR3L, 16 bits, 533 MHz
20  - 1-Gbps Ethernet (RGMII) compliant with IEEE-802.3ab
21  - USB OTG HS
22  - Audio CODEC, with a stereo headset jack, including analog microphone input
23  - 4 user LEDs
24  - 2 user and reset push-buttons, 1 wake-up button
25  - 5 V / 3 A USB Type-CTM power supply input (not provided)
26  - Board connectors:
27
28    - Ethernet RJ45
29    - 4 USB Host Type-A
30    - USB Type-C
31    - DRP MIPI DSI HDMI
32    - Stereo headset jack including analog microphone input
33    - microSD card
34    - GPIO expansion connector (Raspberry Pi® shields capability)
35    - ArduinoTM Uno V3 expansion connectors
36    - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
37      capability: Virtual COM port and debug port
38
39- Board-specific features:
40
41  - 4" TFT 480×800 pixels with LED backlight, MIPI DSI interface, and capacitive
42    touch panel
43  - Wi-Fi® 802.11b/g/n
44  - Bluetooth® Low Energy 4.1
45
46More information about the board can be found at the
47`STM32P157C Discovery website`_.
48
49Hardware
50********
51
52The STM32MP157 SoC provides the following hardware capabilities:
53
54- Core:
55
56  - 32-bit dual-core Arm® Cortex®-A7
57
58    - L1 32-Kbyte I / 32-Kbyte D for each core
59    - 256-Kbyte unified level 2 cache
60    - Arm® NEON™ and Arm® TrustZone®
61
62  - 32-bit Arm® Cortex®-M4 with FPU/MPU
63
64    - Up to 209 MHz (Up to 703 CoreMark®)
65
66- Memories:
67
68  - External DDR memory up to 1 Gbyte.
69  - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM +
70    64 KB of AHB SRAM in backup domain.
71  - Dual mode Quad-SPI memory interface
72  - Flexible external memory controller with up to 16-bit data bus
73
74- Security/safety:
75
76  - Secure boot, TrustZone® peripherals with Cortex®-M4 resources isolation
77
78
79- Clock management:
80
81  - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz
82    LSI oscillator
83  - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
84  - 6 × PLLs with fractional mode
85
86- General-purpose input/outputs:
87
88  - Up to 176 I/O ports with interrupt capability
89
90- Interconnect matrix
91
92- 3 DMA controllers
93
94- Communication peripherals:
95
96  - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
97  - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
98  - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
99  - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
100  - SPDIF Rx with 4 inputs
101  - HDMI-CEC interface
102  - MDIO Slave interface
103  - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
104  - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability
105  - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously
106  - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
107  - 8- to 14-bit camera interface up to 140 Mbyte/s
108  - 6 analog peripherals
109  - 2 × ADCs with 16-bit max. resolution.
110  - 1 × temperature sensor
111  - 2 × 12-bit D/A converters (1 MHz)
112  - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6
113    filters
114  - Internal or external ADC/DAC reference VREF+
115
116- Graphics:
117
118  - 3D GPU: Vivante® - OpenGL® ES 2.0
119  - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps
120  - MIPI® DSI 2 data lanes up to 1 GHz each
121
122- Timers:
123
124  - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
125    (incremental) encoder input
126  - 2 × 16-bit advanced motor control timers
127  - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
128  - 5 × 16-bit low-power timers
129  - RTC with sub-second accuracy and hardware calendar
130  - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
131  - 1 × SysTick Cortex®-M4 timer
132
133- Hardware acceleration:
134
135  - AES 128, 192, 256, TDES
136  - HASH (MD5, SHA-1, SHA224, SHA256), HMAC
137  - 2 × true random number generator (3 oscillators each)
138  - 2 × CRC calculation unit
139
140- Debug mode:
141
142  - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
143  - 8-Kbyte embedded trace buffer
144  - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
145
146More information about STM32P157C can be found here:
147
148- `STM32MP157C on www.st.com`_
149- `STM32MP157C reference manual`_
150
151Supported Features
152==================
153
154The Zephyr stm32mp157c_dk2 board configuration supports the following hardware
155features:
156
157+-----------+------------+-------------------------------------+
158| Interface | Controller | Driver/Component                    |
159+===========+============+=====================================+
160| NVIC      | on-chip    | nested vector interrupt controller  |
161+-----------+------------+-------------------------------------+
162| GPIO      | on-chip    | gpio                                |
163+-----------+------------+-------------------------------------+
164| UART      | on-chip    | serial port-polling;                |
165|           |            | serial port-interrupt               |
166+-----------+------------+-------------------------------------+
167| PINMUX    | on-chip    | pinmux                              |
168+-----------+------------+-------------------------------------+
169| I2C       | on-chip    | i2c                                 |
170+-----------+------------+-------------------------------------+
171| SPI       | on-chip    | spi                                 |
172+-----------+------------+-------------------------------------+
173
174The default configuration can be found in
175:zephyr_file:`boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig`
176
177
178Connections and IOs
179===================
180
181STM32MP157C-DK2 Discovery Board schematic is available here:
182`STM32MP157C Discovery board schematics`_.
183
184
185Default Zephyr Peripheral Mapping:
186----------------------------------
187
188- USART_3 TX/RX : PB10/PB12 (UART console)
189- UART_7 TX/RX : PE8/PE7 (Arduino Serial)
190- I2C5 SCL/SDA : PA11/PA12 (Arduino I2C)
191- SPI4 SCK/MISO/MOSI : PE12/PE13/PE14 (Arduino SPI)
192- SPI5 SCK/MISO/MOSI : PF7/PF8/PF9
193
194System Clock
195------------
196
197The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value
198must match the configured mlhclk_ck frequency.
199
200Serial Port
201-----------
202
203The STM32MP157C-DK2 Discovery board has 8 U(S)ARTs.
204The Zephyr console output is assigned by default to the RAM console to be dumped
205by the Linux Remoteproc Framework on Cortex®-A7 core. In order to keep the UART7
206free for future serial interactions with Arduino shield, the Zephyr UART console
207output is USART3 and is disabled by default. UART console can be enable through
208board's devicetree and stm32mp157c_dk2_defconfig board file (or prj.conf
209project files), and will disable existing RAM console output. Default UART
210console settings are 115200 8N1.
211
212Programming and Debugging
213*************************
214The STM32MP157C doesn't have QSPI flash for the Cortex®-M4  and it needs to be
215started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
216Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset.
217The Cortex®-A7 can perform these steps at bootloader level or after the Linux
218system has booted.
219
220The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at
221address 0x00000000 (RETRAM), the vector table should be loaded at this address
222These are the memory mappings for Cortex®-A7 and Cortex®-M4:
223
224+------------+-----------------------+------------------------+----------------+
225| Region     | Cortex®-A7            | Cortex®-M4             | Size           |
226+============+=======================+========================+================+
227| RETRAM     | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF  | 64KB           |
228+------------+-----------------------+------------------------+----------------+
229| MCUSRAM    | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF  | 384KB          |
230+------------+-----------------------+------------------------+----------------+
231| DDR        | 0xC0000000-0xFFFFFFFF |                        | up to 1 GB     |
232+------------+-----------------------+------------------------+----------------+
233
234
235Refer to `stm32mp157c boot Cortex-M4 firmware`_ wiki page for instruction
236to load and start the Cortex-M4 firmware.
237
238Debugging
239=========
240
241You can debug an application using OpenOCD and GDB. The Solution proposed below
242is based on the attach to a preloaded firmware, available only for a Linux
243environment. The firmware must first be loaded by the Cortex®-A7. Developer
244then attaches the debugger to the running Zephyr using OpenOCD.
245
246Principle is to attach to the firmware already loaded by the Linux.
247
248- Build the sample:
249
250.. code-block:: console
251
252  west build -b stm32mp157c_dk2 samples/hello_world
253
254- Copy the firmware on the target filesystem, load it and start it (`stm32mp157c boot Cortex-M4 firmware`_).
255- Attach to the target:
256
257.. code-block:: console
258
259  west attach
260
261.. _STM32P157C Discovery website:
262   https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-discovery-kits/stm32mp157c-dk2.html
263
264.. _STM32MP157C Discovery board User Manual:
265   https://www.st.com/resource/en/user_manual/dm00591354.pdf
266
267.. _STM32MP157C Discovery board schematics:
268   https://www.st.com/resource/en/schematic_pack/mb1272-dk2-c01_schematic.pdf
269
270.. _STM32MP157C on www.st.com:
271   https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157c.html
272
273.. _STM32MP157C reference manual:
274   https://www.st.com/resource/en/reference_manual/DM00327659.pdf
275
276.. _stm32mp1 developer package:
277   https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK
278
279.. _stm32mp157c boot Cortex-M4 firmware:
280   https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework
281