| /Zephyr-latest/dts/bindings/clock/ |
| D | nxp,kinetis-ke1xf-sim.yaml | 14 clkout-source:
16 description: clkout clock source
18 clkout-divider:
20 description: clkout divider
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| D | nxp,kinetis-sim.yaml | 24 clkout-source:
26 description: clkout clock source
28 clkout-divider:
30 description: clkout divider
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| D | litex,clkout.yaml | 9 compatible: "litex,clkout"
62 exponent for clkout margin
63 effective clkout margin shall be
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| D | litex,clk.yaml | 73 litex,clkout-divide-min:
78 litex,clkout-divide-max:
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | m5stack,stamps3-header.yaml | 17 8 GPIO/CLKOUT0 25 GPIO/CLKOUT/TXD
19 10 GND 23 GPIO/CLKOUT/RXD
20 11 GPIO/SDA1 22 GPIO/CLKOUT
22 13 GPIO/SCL1 20 GPIO/CLKOUT
24 15 GPIO 18 GPIO/CLKOUT
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| D | adi,sdp-120.yaml | 60 50 NC CLKOUT 71
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| /Zephyr-latest/dts/bindings/rtc/ |
| D | microcrystal,rv-8263-c8.yaml | 17 clkout:
30 Enable CLKOUT at given frequency. When disabled, CLKOUT pin is LOW.
31 The default is 0 and corresponds to the disable the CLKOUT signal.
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| D | microcrystal,rv3028.yaml | 13 clkout-frequency:
23 Frequency of the CLKOUT signal in Hertz (Hz). If omitted, the CLKOUT pin is LOW.
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| D | nxp,pcf8523.yaml | 27 clkout-frequency:
40 Frequency of the CLKOUT signal in Hertz (Hz). Default is 32768 Hz which corresponds to the
42 disable the CLKOUT signal (High-Z).
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| /Zephyr-latest/dts/bindings/can/ |
| D | espressif,esp32-twai.yaml | 26 clkout-divider:
29 Clock divider for the CLKOUT signal. If not set, the CLKOUT signal is turned off.
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| /Zephyr-latest/boards/nxp/twr_ke18f/ |
| D | Kconfig | 9 bool "CLKOUT signal on FlexIO header"
12 Enable the CLKOUT signal on FlexIO header pin 7 (PTE10).
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| D | twr_ke18f.dts | 153 clkout-source = <1>;
154 clkout-divider = <0>;
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_litex.h | 63 BUILD_ASSERT(CLKOUT_ID(N) < NCLKOUT, "Invalid CLKOUT index"); \
75 /* Devicetree clkout defines */
226 struct litex_clk_clkout_addr clkout[CLKOUT_MAX]; member
244 uint8_t *update_clkout; /* which clkout needs update */
253 struct litex_clk_params config; /* real CLKOUT settings */
254 struct litex_clk_params ts_config; /* CLKOUT settings to set */
255 struct litex_clk_div_params div; /* CLKOUT configuration groups*/
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| D | clock_control_litex.c | 26 static struct litex_clk_clkout *clkouts;/* clkout array for whole driver */
52 m.clkout[5].reg1 = CLKOUT5_REG1; in litex_clk_regs_addr_init()
53 m.clkout[5].reg2 = CLKOUT5_REG2; in litex_clk_regs_addr_init()
55 m.clkout[i].reg1 = addr; in litex_clk_regs_addr_init()
57 m.clkout[i].reg2 = addr; in litex_clk_regs_addr_init()
353 /* Return dividers of given CLKOUT */
363 ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg1, &div); in litex_clk_get_clkout_divider()
367 ret = litex_clk_get_DO(drp_addr.clkout[clkout_nr].reg2, &frac); in litex_clk_get_clkout_divider()
412 static void litex_clk_print_clkout_regs(uint8_t clkout, uint8_t reg1, in litex_clk_print_clkout_regs() argument
418 sprintf(reg_name, "CLKOUT%u REG1", clkout); in litex_clk_print_clkout_regs()
[all …]
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| D | clock_control_lpc11u6x.h | 94 volatile uint32_t clk_out_sel; /* CLKOUT source select */
95 volatile uint32_t clk_out_uen; /* CLKOUT source update */
96 volatile uint32_t clk_out_div; /* CLKOUT divider */
108 volatile const uint32_t pio_por_cap[3]; /* CLKOUT source select */
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| /Zephyr-latest/tests/drivers/build_all/rtc/ |
| D | i2c_devices.overlay | 53 clkout-frequency = <1>;
64 clkout = <4096>;
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| /Zephyr-latest/dts/riscv/ |
| D | riscv32-litex-vexriscv.dtsi | 333 compatible = "litex,clkout";
346 compatible = "litex,clkout";
386 litex,clkout-divide-min = <1>;
387 litex,clkout-divide-max = <126>;
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| /Zephyr-latest/drivers/rtc/ |
| D | rtc_rv8263.c | 74 uint32_t clkout; member
308 temp = config->clkout; in rv8263c8_init()
309 LOG_DBG("Configure ClkOut: %u", temp); in rv8263c8_init()
318 LOG_DBG("Configure ClkOut: %u", temp); in rv8263c8_init()
706 .clkout = DT_INST_ENUM_IDX(inst, clkout), \
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| D | rtc_pcf8523.c | 231 /* Disable CLKOUT */ in pcf8523_int1_enable_unlocked()
234 /* Enable CLKOUT */ in pcf8523_int1_enable_unlocked()
810 * Defer GPIO interrupt configuration due to INT1/CLKOUT pin sharing. This allows in pcf8523_init()
811 * using the CLKOUT square-wave signal for RTC calibration when no alarm/update in pcf8523_init()
876 /* Disable CLKOUT */ in pcf8523_init()
879 /* Configure CLKOUT frequency */ in pcf8523_init()
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| /Zephyr-latest/dts/arm/renesas/ra/ra4/ |
| D | r7fa4w1ad2cng.dtsi | 168 clkout: clkout { label
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| D | r7fa4e2b93cfm.dtsi | 185 clkout: clkout { label
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| /Zephyr-latest/dts/arm/renesas/ra/ra2/ |
| D | r7fa2a1xh.dtsi | 170 clkout: clkout { label
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| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | r7fa6m1ad3cfp.dtsi | 163 clkout: clkout { label
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| D | r7fa6e2bx.dtsi | 194 clkout: clkout { label
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| /Zephyr-latest/samples/drivers/clock_control_litex/src/ |
| D | main.c | 75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n", in litex_clk_test_getters()
78 printf("CLKOUT%d: get_rate:%d\n", i, rate); in litex_clk_test_getters()
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