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/Zephyr-latest/soc/cdns/xtensa_sample_controller/include/
Dxtensa-sample-controller.ld27 iram0_1_seg : org = 0x40000178, len = 0x8
29 iram0_3_seg : org = 0x400001B8, len = 0x8
31 iram0_5_seg : org = 0x400001F8, len = 0x8
33 iram0_7_seg : org = 0x40000238, len = 0x8
35 iram0_9_seg : org = 0x40000278, len = 0x8
37 iram0_11_seg : org = 0x400002B8, len = 0x8
39 iram0_13_seg : org = 0x400002F8, len = 0x8
41 iram0_15_seg : org = 0x40000338, len = 0x8
188 .dram1.rodata : ALIGN(4)
195 .dram1.literal : ALIGN(4)
[all …]
/Zephyr-latest/arch/arm64/core/
Dearly_mem_funcs.S34 and x8, x1, #0xff
36 mul x8, x8, x9
41 str x8, [x0], #8
45 cbz x2, 4f
52 4: ret
59 orr x8, x1, x0
60 tst x8, #0x7
68 ldr x8, [x1], #8
71 str x8, [x0], #8
75 cbz x2, 4f
[all …]
/Zephyr-latest/soc/neorv32/
Dreset.S54 la x8, __io_start
56 1: sw x0, 0(x8)
57 addi x8, x8, 4
58 bne x8, x9, 1b
68 .balign 4
71 addi x5, x5, 4
/Zephyr-latest/drivers/spi/
Dspi_pw.h56 /* Frame format sscr0[5:4] */
57 #define PW_SPI_FRF_MOTOROLA (~(0x3 << 4))
68 #define PW_SPI_SCR_SHIFT 0x8
75 #define PW_SPI_CTRL1_SPH_BIT BIT(4)
83 /* [4:3] phase & polarity mask */
89 #define PW_SPI_SSSR_BSY_BIT BIT(4)
100 #define PW_SPI_SITF_HWM_8_ENTRY 0x8
119 #define PW_SPI_SITF_WMRF_8_ENTRY 0x8
126 #define PW_SPI_SIRF_SIRFL_SHIFT 0x8
130 #define PW_SPI_SITF_LWMTF_SHIFT 0x8
[all …]
/Zephyr-latest/samples/net/sockets/can/
Dsample.yaml24 - "(.*)\\[0|3\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8"
34 - "(.*)\\[0|3\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8"
36 - "(.*)\\[1|4\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8"
/Zephyr-latest/drivers/ethernet/
Deth_smsc91x_priv.h36 #define ECR_MULCOL_MASK GENMASK(7, 4) /* Multiple collisions */
40 /* Bank 0, Offset 0x8: Memory information register */
41 #define MIR 0x8
51 #define RPCR_LSB_MASK GENMASK(4, 2)
72 #define IAR4 0x8
86 #define MMUCR_CMD_RELEASE 4 /* Remove and release from RX FIFO */
114 /* Bank2, Offset 0x8: Data register */
115 #define DATA0 0x8
132 /* Bank 3, Offset 0x8: Management interface register */
133 #define MGMT 0x8
[all …]
/Zephyr-latest/soc/cdns/sample_controller32/include/
Dxtensa-sample-controller32.ld31 #define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(4);
32 #define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4)
51 iram0_1_seg : org = 0x40000178, len = 0x8
53 iram0_3_seg : org = 0x400001B8, len = 0x8
55 iram0_5_seg : org = 0x400001F8, len = 0x8
57 iram0_7_seg : org = 0x40000238, len = 0x8
59 iram0_9_seg : org = 0x40000278, len = 0x8
61 iram0_11_seg : org = 0x400002B8, len = 0x8
63 iram0_13_seg : org = 0x400002F8, len = 0x8
65 iram0_15_seg : org = 0x40000338, len = 0x8
[all …]
/Zephyr-latest/soc/litex/litex_vexriscv/
Dsoc.h42 | (sys_read8(addr + 0x8) << 8) in litex_read32()
56 | ((uint64_t)sys_read8(addr + 0x8) << 40) in litex_read64()
97 sys_write8(value >> 8, addr + 0x8); in litex_write32()
111 sys_write8(value >> 40, addr + 0x8); in litex_write64()
129 * Size is in bytes and meaningful are 1, 2 or 4
130 * Address must be aligned to 4 bytes
141 case 4: in litex_write()
151 * Size is in bytes and meaningful are 1, 2 or 4
152 * Address must be aligned to 4 bytes
161 case 4: in litex_read()
/Zephyr-latest/drivers/sensor/bosch/bme680/
DKconfig32 bool "x8"
50 bool "x8"
68 bool "x8"
83 bool "4"
/Zephyr-latest/drivers/sensor/bosch/bme280/
DKconfig45 bool "x8"
63 bool "x8"
81 bool "x8"
120 bool "4"
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg24-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
22 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4)
27 #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 21, 1, 2, 4)
29 #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 21, 1, 4, 6)
34 #define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 29, 1, 2, 4)
36 #define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 29, 1, 4, 6)
52 #define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 50, 1, 3, 4)
53 #define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 50, 1, 4, 5)
70 #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 70, 1, 3, 4)
71 #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 70, 1, 4, 5)
[all …]
Dxg23-pinctrl.h22 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 22, 1, 2, 4)
27 #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 33, 1, 2, 4)
29 #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 33, 1, 4, 6)
34 #define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 41, 1, 2, 4)
36 #define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 41, 1, 4, 6)
41 #define SILABS_DBUS_EUSART2_RX(port, pin) SILABS_DBUS(port, pin, 49, 1, 2, 4)
43 #define SILABS_DBUS_EUSART2_TX(port, pin) SILABS_DBUS(port, pin, 49, 1, 4, 6)
59 #define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 70, 1, 3, 4)
60 #define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 70, 1, 4, 5)
74 #define SILABS_DBUS_LESENSE_CH3OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 3, 4)
[all …]
Dxg22-pinctrl.h16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
17 #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 4, 1, 1, 3)
18 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 4, 1, 2, 4)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1)
35 #define SILABS_DBUS_EUART0_TX(port, pin) SILABS_DBUS(port, pin, 32, 1, 1, 4)
42 #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 38, 1, 3, 4)
43 #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 38, 1, 4, 5)
63 #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 61, 1, 3, 4)
64 #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 61, 1, 4, 5)
80 #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 79, 1, 3, 4)
[all …]
Dxg27-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4)
25 #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4)
27 #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6)
46 #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 44, 1, 3, 4)
47 #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 44, 1, 4, 5)
67 #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 67, 1, 3, 4)
68 #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 67, 1, 4, 5)
84 #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 85, 1, 3, 4)
85 #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 85, 1, 4, 5)
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo3_blue.dtsi185 ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
196 ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
205 interrupts = <4 0>;
207 ambiq,pwrcfg = <&pwrcfg 0x8 0>;
217 ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
227 ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
237 ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
247 ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
257 ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
267 ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
[all …]
Dambiq_apollo3p_blue.dtsi203 ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
214 ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
223 interrupts = <4 0>;
225 ambiq,pwrcfg = <&pwrcfg 0x8 0>;
235 ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
245 ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
255 ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
265 ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
275 ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
285 ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dso.h28 #define LSM6DSO_DT_FS_1000DPS 4
40 #define LSM6DSO_DT_ODR_1667Hz 0x8
Dtmag5273.h24 #define TMAG5273_DT_AXIS_XYX 0x8
60 #define TMAG5273_DT_ANGLE_MAG_RUNTIME 4
71 #define TMAG5273_DT_AVERAGING_16X 4
79 #define TMAG5273_DT_SLEEPTIME_20MS 4
/Zephyr-latest/lib/crc/
Dcrc4_sw.c17 crc ^= ((src[i] >> (4 * (1 - j))) & 0xf); in crc4()
19 for (k = 0; k < 4; k++) { in crc4()
27 if (crc & 0x8) { in crc4()
47 index = seed ^ ((src[i] >> (4*(1-j))) & 0xf); in crc4_ti()
48 seed = (lookup[index >> 1] >> (1 - (index & 1)) * 4) & 0xf; in crc4_ti()
/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Darm64.py22 X4 = 4
26 X8 = 8 variable in RegNum
82 self.registers[RegNum.X4] = tu[4]
86 self.registers[RegNum.X8] = tu[8]
/Zephyr-latest/boards/snps/em_starterkit/
Dpmodmux.c20 * 32-bits, offset 0x8, SPI_MAP_CTRL[0] selects the mode of operation of the SPI
27 * 32-bits, offset 0x8, This register controls the mapping of the UART signals
37 #define PM2_OFFSET (4)
65 /* Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
67 /* Pmod1[4:1] are connected to DW UART0 signals */
75 * Pmod2[4:1] are connected to DW GPIO Port C[15:12],
79 /* connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */
82 * Pmod3[4:1] are connected to DW GPIO Port C[19:16],
87 * Pmod3[4:3] are connected to DW I2C signals,
93 * Pmod4[4:1] are connected to DW GPIO Port C[23:20],
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dmchp-xec-pinctrl.h21 #define MCHP_AFMAX 0x8
39 #define MCHP_XEC_DRV_STR0_1X 0x1 /* 2 or 4(PIO-24) mA */
40 #define MCHP_XEC_DRV_STR0_2X 0x2 /* 4 or 8(PIO-24) mA */
48 #define MCHP_XEC_PINMUX_PIN_POS 4
57 * b[8:4] = pin position in bank
/Zephyr-latest/soc/amd/acp_6_0/adsp/
Dmemory.h20 #define MEM_RESET_LIT_SIZE 0x8
118 #define HEAP_RT_COUNT512 4
150 #define SOF_MEM_RESET_LIT_SIZE 0x8
153 #define SOF_MEM_RO_SIZE 0x8
/Zephyr-latest/dts/bindings/clock/
Dst,stm32f105-pll-clock.yaml40 - 4 # x4
44 - 8 # x8
/Zephyr-latest/samples/modules/canopennode/objdict/
Dobjdict.eds35 NrOfRXPDO=4
36 NrOfTXPDO=4
88 DefaultValue=4
132 4=0x1006
180 ObjectType=0x8
321 ObjectType=0x8
345 ObjectType=0x8
396 ObjectType=0x8
406 DefaultValue=4
465 ObjectType=0x8
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