Lines Matching +full:4 +full:x8

36 #define ECR_MULCOL_MASK	  GENMASK(7, 4)	  /* Multiple collisions */
40 /* Bank 0, Offset 0x8: Memory information register */
41 #define MIR	      0x8
51 #define RPCR_LSB_MASK	  GENMASK(4, 2)
72 #define IAR4 0x8
86 #define MMUCR_CMD_RELEASE     4		    /* Remove and release from RX FIFO */
114 /* Bank2, Offset 0x8: Data register */
115 #define DATA0 0x8
132 /* Bank 3, Offset 0x8: Management interface register */
133 #define MGMT	  0x8
141 #define REV_CHIP_MASK GENMASK(7, 4)