Lines Matching +full:4 +full:x8
16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4)
25 #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4)
27 #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6)
46 #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 44, 1, 3, 4)
47 #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 44, 1, 4, 5)
67 #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 67, 1, 3, 4)
68 #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 67, 1, 4, 5)
84 #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 85, 1, 3, 4)
85 #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 85, 1, 4, 5)
91 #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4)
92 #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5)
98 #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4)
99 #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5)
105 #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4)
106 #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5)
112 #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4)
113 #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5)
118 #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 125, 1, 2, 4)
120 #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 6)
125 #define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 133, 1, 2, 4)
127 #define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 133, 1, 4, 6)
138 #define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
189 #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
216 #define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8)
242 #define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
268 #define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8)
294 #define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
320 #define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8)
346 #define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
410 #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
436 #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
488 #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
502 #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
517 #define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
543 #define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
701 #define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
715 #define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
729 #define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
744 #define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8)
770 #define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
796 #define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
823 #define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
837 #define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
851 #define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
865 #define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
879 #define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
893 #define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
979 #define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
1005 #define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
1031 #define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
1057 #define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
1084 #define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1110 #define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1136 #define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1162 #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1188 #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1214 #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
1241 #define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
1267 #define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
1293 #define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
1319 #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
1345 #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
1371 #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
1398 #define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
1412 #define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
1426 #define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
1440 #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
1454 #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
1468 #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
1556 #define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
1570 #define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
1584 #define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
1598 #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
1612 #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
1626 #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
1641 #define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
1667 #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
1693 #define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
1719 #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
1745 #define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
1771 #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
1798 #define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8)
1812 #define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
1826 #define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8)
1840 #define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
1854 #define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8)
1868 #define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)