Lines Matching +full:4 +full:x8
16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
17 #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 4, 1, 1, 3)
18 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 4, 1, 2, 4)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1)
35 #define SILABS_DBUS_EUART0_TX(port, pin) SILABS_DBUS(port, pin, 32, 1, 1, 4)
42 #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 38, 1, 3, 4)
43 #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 38, 1, 4, 5)
63 #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 61, 1, 3, 4)
64 #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 61, 1, 4, 5)
80 #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 79, 1, 3, 4)
81 #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 79, 1, 4, 5)
87 #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 87, 1, 3, 4)
88 #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 87, 1, 4, 5)
94 #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 95, 1, 3, 4)
95 #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 95, 1, 4, 5)
101 #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 103, 1, 3, 4)
102 #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 103, 1, 4, 5)
108 #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 111, 1, 3, 4)
109 #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 111, 1, 4, 5)
114 #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 119, 1, 2, 4)
116 #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 119, 1, 4, 6)
121 #define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 127, 1, 2, 4)
123 #define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 127, 1, 4, 6)
158 #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
222 #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
248 #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
300 #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
314 #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
329 #define EUART0_RTS_PA8 SILABS_DBUS_EUART0_RTS(0x0, 0x8)
355 #define EUART0_TX_PA8 SILABS_DBUS_EUART0_TX(0x0, 0x8)
381 #define EUART0_CTS_PA8 SILABS_DBUS_EUART0_CTS(0x0, 0x8)
407 #define EUART0_RX_PA8 SILABS_DBUS_EUART0_RX(0x0, 0x8)
434 #define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
460 #define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
618 #define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
632 #define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
646 #define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
661 #define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8)
687 #define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
713 #define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
740 #define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
754 #define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
768 #define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
782 #define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
796 #define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
810 #define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
896 #define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
922 #define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
948 #define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
974 #define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
1001 #define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1027 #define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1053 #define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1079 #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1105 #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1131 #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
1158 #define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
1184 #define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
1210 #define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
1236 #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
1262 #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
1288 #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
1315 #define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
1329 #define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
1343 #define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
1357 #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
1371 #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
1385 #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
1473 #define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
1487 #define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
1501 #define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
1515 #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
1529 #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
1543 #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
1558 #define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
1584 #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
1610 #define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
1636 #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
1662 #define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
1688 #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
1715 #define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8)
1729 #define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
1743 #define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8)
1757 #define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
1771 #define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8)
1785 #define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)