| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ti-cc32xx-pinctrl.h | 19 * - 4: Enable open-drain flag.
32 #define TI_CC32XX_PIN_POS 16U
34 #define TI_CC32XX_MUX_POS 0U
53 #define GPIO10_P1 TI_CC32XX_PINMUX(1U, 0U)
54 #define I2C_SCL_P1 TI_CC32XX_PINMUX(1U, 1U)
55 #define GT_PWM06_P1 TI_CC32XX_PINMUX(1U, 3U)
56 #define UART1_TX_P1 TI_CC32XX_PINMUX(1U, 7U)
57 #define SDCARD_CLK_P1 TI_CC32XX_PINMUX(1U, 6U)
58 #define GT_CCP01_P1 TI_CC32XX_PINMUX(1U, 12U)
60 #define GPIO11_P2 TI_CC32XX_PINMUX(2U, 0U)
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| /Zephyr-latest/drivers/can/ |
| D | can_sja1000_priv.h | 13 #define CAN_SJA1000_MOD (0U)
14 #define CAN_SJA1000_CMR (1U)
15 #define CAN_SJA1000_SR (2U)
16 #define CAN_SJA1000_IR (3U)
17 #define CAN_SJA1000_IER (4U)
18 #define CAN_SJA1000_BTR0 (6U)
19 #define CAN_SJA1000_BTR1 (7U)
20 #define CAN_SJA1000_OCR (8U)
21 #define CAN_SJA1000_ALC (11U)
22 #define CAN_SJA1000_ECC (12U)
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | kinetis_scg.h | 11 #define KINETIS_SCG_SOSC_MODE_EXT 0U
12 #define KINETIS_SCG_SOSC_MODE_LOW_POWER 4U
13 #define KINETIS_SCG_SOSC_MODE_HIGH_GAIN 12U
16 #define KINETIS_SCG_CORESYS_CLK 0U
17 #define KINETIS_SCG_BUS_CLK 1U
18 #define KINETIS_SCG_FLEXBUS_CLK 2U
19 #define KINETIS_SCG_FLASH_CLK 3U
20 #define KINETIS_SCG_SOSC_CLK 4U
21 #define KINETIS_SCG_SIRC_CLK 5U
22 #define KINETIS_SCG_FIRC_CLK 6U
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| D | gd32vf103-clocks.h | 29 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
30 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
35 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
38 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
39 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
40 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
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| D | gd32e10x-clocks.h | 30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
39 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
40 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
41 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
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| D | gd32f403-clocks.h | 30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U)
37 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
40 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
41 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
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| /Zephyr-latest/samples/basic/blinky_pwm/src/ |
| D | main.c | 19 #define MIN_PERIOD PWM_SEC(1U) / 128U
20 #define MAX_PERIOD PWM_SEC(1U)
26 uint8_t dir = 0U; in main()
41 * Keep its value at least MIN_PERIOD * 4 to make sure in main()
46 while (pwm_set_dt(&pwm_led0, max_period, max_period / 2U)) { in main()
47 max_period /= 2U; in main()
48 if (max_period < (4U * MIN_PERIOD)) { in main()
51 4U * MIN_PERIOD); in main()
56 printk("Done calibrating; maximum/minimum periods %u/%lu nsec\n", in main()
61 ret = pwm_set_dt(&pwm_led0, period, period / 2U); in main()
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| /Zephyr-latest/include/zephyr/bluetooth/audio/ |
| D | bap_lc3_preset.h | 61 BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 26u, 1, \
63 BT_BAP_QOS_CFG_UNFRAMED(7500u, 26u, 2u, 8u, 40000u))
73 BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 30U, 1, \
75 BT_BAP_QOS_CFG_UNFRAMED(10000u, 30u, 2u, 10u, 40000u))
85 BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 30U, 1, \
87 BT_BAP_QOS_CFG_UNFRAMED(7500u, 30u, 2u, 8u, 40000u))
99 BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 40U, 1, \
101 BT_BAP_QOS_CFG_UNFRAMED(10000u, 40u, 2u, 10u, 40000u))
111 BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 45U, 1, \
113 BT_BAP_QOS_CFG_UNFRAMED(7500u, 45u, 2u, 8u, 40000u))
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| /Zephyr-latest/soc/microchip/mec/common/ |
| D | soc_pins.h | 15 #define MCHP_GPIO_000 (0U)
16 #define MCHP_GPIO_001 (1U)
17 #define MCHP_GPIO_002 (2U)
18 #define MCHP_GPIO_003 (3U)
19 #define MCHP_GPIO_004 (4U)
20 #define MCHP_GPIO_005 (5U)
21 #define MCHP_GPIO_006 (6U)
22 #define MCHP_GPIO_007 (7U)
23 #define MCHP_GPIO_010 (8U)
24 #define MCHP_GPIO_011 (9U)
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | soc_espi_saf_v2.h | 17 #define MCHP_SAF_MAX_FLASH_DEVICES 2U
28 #define MCHP_SAF_FLASH_POLL_INTERVAL 0u
29 #define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8u
30 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2u
31 #define MCHP_SAF_FLASH_SUS_CHK_DELAY 0u
43 #define MCHP_SAF_QMSPI_CLK_DIV 4u
51 #define MCHP_SAF_CS0_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4)
52 #define MCHP_SAF_CS1_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4)
58 #define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6u
59 #define MCHP_SAF_QMSPI_CS0_START_DESCR 0u
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| /Zephyr-latest/samples/drivers/jesd216/src/ |
| D | main.c | 42 [JESD216_MODE_114] = "1-1-4",
45 [JESD216_MODE_144] = "1-4-4",
48 [JESD216_MODE_444] = "4-4-4",
61 [JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_3B4B] = "3- or 4-Byte", in summarize_dw1()
62 [JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B] = "4-Byte only", in summarize_dw1()
76 printf("4-KiBy erase: %s\n", bsersz[(dw1 & JESD216_SFDP_BFP_DW1_BSERSZ_MASK) in summarize_dw1()
91 printf("Support %s: instr %02Xh, %u mode clocks, %u waits\n", in summarize_dw1()
101 printf("Flash density: %u bytes\n", (uint32_t)(jesd216_bfp_density(bfp) / 8)); in summarize_dw2()
116 printf("ET%u: instr %02Xh for %u By", idx, etype.cmd, in summarize_dw89()
119 printf("; typ %u ms, max %u ms", in summarize_dw89()
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| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_global_cfg.h | 22 #define MCHP_GCFG_DEV_ID_REG32_OFS 28u
32 #define MCHP_GCFG_REV_A1 2u
33 #define MCHP_GCFG_REV_B0 3u
38 * bits[7:4] = chip family
43 #define MCHP_GCFG_SUB_ID_PKG_UNDEF 0u
44 #define MCHP_GCFG_SUB_ID_PKG_64_PIN 1u
45 #define MCHP_GCFG_SUB_ID_PKG_84_PIN 2u
46 #define MCHP_GCFG_SUB_ID_PKG_128_PIN 3u
47 #define MCHP_GCFG_SUB_ID_PKG_144_PIN 4u
48 #define MCHP_GCFG_SUB_ID_PKG_176_PIN 7u
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| D | mec_timers.h | 20 #define MCHP_BTMR_BASE_FREQ 48000000u
48 #define MCHP_BTMR_INTDIS 0u
54 #define MCHP_BTMR_CTRL_PRESCALE_POS 16u
66 #define MCHP_BTMR_CTRL_HALT_POS 7u
67 #define MCHP_BTMR_CTRL_RELOAD_POS 6u
68 #define MCHP_BTMR_CTRL_START_POS 5u
69 #define MCHP_BTMR_CTRL_SRESET_POS 4u
70 #define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u
71 #define MCHP_BTMR_CTRL_COUNT_DIR_POS 2u
72 #define MCHP_BTMR_CTRL_ENABLE_POS 0u
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| /Zephyr-latest/boards/nxp/vmu_rt1170/ |
| D | flexspi_nor_config.c | 53 .csHoldTime = 1u,
54 .csSetupTime = 1u,
57 .sflashA1Size = 64u * 1024u * 1024u,
67 .pageSize = 256u,
68 .sectorSize = 4u * 1024u,
69 .blockSize = 64u * 1024u,
92 (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable)
93 | (1u << kFlexSpiMiscOffset_DdrModeEnable),
97 .sflashA1Size = 64ul * 1024u * 1024u,
98 .busyOffset = 0u,
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_espi_vw.h | 15 #define ESPI_M2SW0_OFS 0u
18 #define ESPI_M2SW0_MTOS_SRC_POS 8u
21 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0u
25 #define ESPI_M2SW0_MTOS_STATE_POS 12u
29 #define ESPI_M2SW1_OFS 4u
39 /* 0 <= n < 4 */
40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
44 #define ESPI_M2SW2_OFS 8u
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| D | mec172x_qspi.h | 13 #define QMPSPI_HW_VER 4u
17 #define MCHP_QMSPI_MAX_DESCR 16u
19 #define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 96000000u
21 ((MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ) / 1000u)
22 #define MCHP_QMSPI_MIN_FREQ_KHZ (MCHP_QMSPI_MAX_FREQ_KHZ / 256u)
25 #define MCHP_QMSPI_SPI_MODE0 0u
34 #define MCHP_QMSPI_TX_DMA_REQ_ID 10u
35 #define MCHP_QMSPI_RX_DMA_REQ_ID 11u
38 #define MCHP_QMSPI_TX_FIFO_LEN 8u
39 #define MCHP_QMSPI_RX_FIFO_LEN 8u
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| D | mec172x_ecia.h | 16 #define MCHP_FIRST_GIRQ_NOS 8u
17 #define MCHP_LAST_GIRQ_NOS 26u
23 #define MCHP_ECIA_GIRQ_CLK_WAKE_ONLY 22u
36 #define MCHP_NVIC_NUM_PRI_BITS 3u
37 #define MCHP_NVIC_PRI_LO_VAL 7u
44 #define MCHP_NUM_NVIC_REGS 6u
155 #define MCHP_GPIO_0144_GIRQ_POS 4
183 #define MCHP_GPIO_0144_GIRQ_BIT BIT(4)
213 #define MCHP_GPIO_0104_GIRQ_POS 4
244 #define MCHP_GPIO_0104_GIRQ_BIT BIT(4)
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| D | mec172x_ecs.h | 34 #define MCHP_ECS_DCTRL_DBG_EN_POS 0u
36 #define MCHP_ECS_DCTRL_MODE_POS 1u
41 #define MCHP_ECS_DCTRL_DBG_MODE_POS 1u
43 #define MCHP_ECS_DCTRL_MODE_SWD SHLU32(0x02u, 1u)
44 #define MCHP_ECS_DCTRL_MODE_SWD_SWV SHLU32(0x01u, 1u)
45 #define MCHP_ECS_DCTRL_PUEN_POS 3u
47 #define MCHP_ECS_DCTRL_BSCAN_POS 4u
78 #define MCHP_ECS_JTCC_CLK_DFLT 3u
79 #define MCHP_ECS_JTCC_CLK_24M 1u
80 #define MCHP_ECS_JTCC_CLK_12M 2u
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_gd32.c | 20 #define GD32_CLOCK_ID_OFFSET(id) (((id) >> 6U) & 0xFFU)
28 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U,
32 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,
36 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,
135 for (size_t i = 0U; i < ARRAY_SIZE(timer_ids); i++) { in clock_control_gd32_get_rate()
149 * TIMERSEL setting (2 if TIMERSEL=0, 4 if TIMERSEL=1). Above in clock_control_gd32_get_rate()
151 * domain clock CK_APB{1,2} (2 if TIMERSEL=0, 4 if TIMERSEL=1). in clock_control_gd32_get_rate()
155 if ((cfg1 & RCU_CFG1_TIMERSEL_MSK) == 0U) { in clock_control_gd32_get_rate()
156 if (psc <= 2U) { in clock_control_gd32_get_rate()
159 *rate *= 2U; in clock_control_gd32_get_rate()
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| /Zephyr-latest/drivers/flash/ |
| D | flash_gd32_v3.c | 25 {.pages_count = 4, .pages_size = KB(16)},
31 {.pages_count = 4, .pages_size = KB(16)},
37 {.pages_count = 4, .pages_size = KB(16)},
40 {.pages_count = 4, .pages_size = KB(16)},
46 {.pages_count = 4, .pages_size = KB(16)},
49 {.pages_count = 4, .pages_size = KB(16)},
52 {.pages_count = 4, .pages_size = KB(256)},
64 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 11U,
65 16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U, 24U, 25U, 26U, 27U,
66 12U, 13U, 14U, 15U
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| /Zephyr-latest/drivers/usb/uhc/ |
| D | uhc_max3421e.h | 12 #define MAX3421E_MAX_EP_SIZE 64U
16 #define MAX3421E_CMD_REG_SHIFT 3U
18 #define MAX3421E_CMD_DIR_RD 0U
30 #define MAX3421E_REG_RCVFIFO 1U
33 #define MAX3421E_REG_SNDFIFO 2U
36 #define MAX3421E_REG_SUDFIFO 4U
39 #define MAX3421E_REG_RCVBC 6U
43 #define MAX3421E_REG_SNDBC 7U
47 #define MAX3421E_REG_USBIRQ 13U
53 #define MAX3421E_REG_USBIEN 14U
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| /Zephyr-latest/drivers/sensor/ti/tmag5170/ |
| D | tmag5170.c | 45 #define TMAG5170_CONV_AVG_POS 12U
46 #define TMAG5170_CONV_AVG_MASK (BIT_MASK(3U) << TMAG5170_CONV_AVG_POS)
50 #define TMAG5170_MAG_TEMPCO_POS 8U
51 #define TMAG5170_MAG_TEMPCO_MASK (BIT_MASK(2U) << TMAG5170_MAG_TEMPCO_POS)
55 #define TMAG5170_OPERATING_MODE_POS 4U
56 #define TMAG5170_OPERATING_MODE_MASK (BIT_MASK(3U) << TMAG5170_OPERATING_MODE_POS)
60 #define TMAG5170_T_CH_EN_POS 3U
61 #define TMAG5170_T_CH_EN_MASK (BIT_MASK(1U) << TMAG5170_T_CH_EN_POS)
65 #define TMAG5170_T_RATE_POS 2U
66 #define TMAG5170_T_RATE_MASK (BIT_MASK(1U) << TMAG5170_T_RATE_POS)
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/ |
| D | lll_chan.c | 41 if ((chan_map[chan_next >> 3] & (1 << (chan_next % 8))) == 0U) { in lll_chan_sel_1()
80 if ((chan_map[chan_next >> 3] & (1 << (chan_next % 8))) == 0U) { in lll_chan_sel_2()
110 if ((chan_map[chan_idx >> 3] & (1 << (chan_idx % 8))) == 0U) { in lll_chan_iso_event()
156 * Channel Selection algorithm #2, and Section 4.5.8.3.4 Event mapping to used
164 chan_next = 0U; in chan_sel_remap()
165 byte_count = 5U; in chan_sel_remap()
171 bit_count = 8U; in chan_sel_remap()
174 if (chan_index == 0U) { in chan_sel_remap()
215 return ((uint32_t)a * 17U + b) & 0xFFFF; in chan_mam()
225 for (iterate = 0U; iterate < 3; iterate++) { in chan_prn_s()
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| /Zephyr-latest/arch/x86/core/ |
| D | legacy_bios.c | 9 #define DATA_SIZE_K(n) (n * 1024u)
25 for (int i = 0; i < search_length / 8u; i++) { in bios_search_rsdp_buff()
28 return (search_phy_add + (i * 8u)); in bios_search_rsdp_buff()
41 k_mem_map_phys_bare(&zero_page_base, 0, DATA_SIZE_K(4u), 0); in bios_acpi_rsdp_get()
43 search_phy_add = (uintptr_t)((*(uint16_t *)bios_ext_data) << 4u); in bios_acpi_rsdp_get()
44 k_mem_unmap_phys_bare(zero_page_base, DATA_SIZE_K(4u)); in bios_acpi_rsdp_get()
47 rsdp_phy_add = bios_search_rsdp_buff(search_phy_add, DATA_SIZE_K(1u)); in bios_acpi_rsdp_get()
52 return (void *)bios_search_rsdp_buff(BIOS_RODATA_ADD, DATA_SIZE_K(128u)); in bios_acpi_rsdp_get()
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| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | soc_espi_saf_v1.h | 18 #define MCHP_SAF_MAX_FLASH_DEVICES 2U
29 #define MCHP_SAF_FLASH_POLL_INTERVAL 0U
30 #define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8U
31 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2U
32 #define MCHP_SAF_FLASH_SUS_CHK_DELAY 0U
43 #define MCHP_SAF_QMSPI_CLK_DIV 2U
48 #define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6U
49 #define MCHP_SAF_QMSPI_CS0_START_DESCR 0U
54 #define MCHP_SAF_CM_EXIT_START_DESCR 12U
55 #define MCHP_SAF_CM_EXIT_LAST_DESCR 13U
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