Lines Matching +full:4 +full:u

15 #define ESPI_M2SW0_OFS			0u
18 #define ESPI_M2SW0_MTOS_SRC_POS		8u
21 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST	0u
25 #define ESPI_M2SW0_MTOS_STATE_POS	12u
29 #define ESPI_M2SW1_OFS			4u
39 /* 0 <= n < 4 */
40 #define ESPI_M2SW1_SRC_SEL_POS(n)	((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n)	SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v)	SHLU32(((v) & 0xfu), ((n) * 8u))
44 #define ESPI_M2SW2_OFS			8u
48 #define ESPI_M2SW2_SRC1_POS		8u
50 #define ESPI_M2SW2_SRC2_POS		16u
52 #define ESPI_M2SW2_SRC3_POS		24u
54 /* 0 <= n < 4 */
55 #define ESPI_M2SW2_SRC_POS(n)		((n) * 8u)
56 #define ESPI_M2SW2_SRC_MASK(n)		SHLU32(0xfu, ((n) * 8u))
57 #define ESPI_M2SW2_SRC_VAL(n, v)	SHLU32(((v) & 0xfu), ((n) * 8u))
71 #define ESPI_IRQ_SEL_DIS	4
82 #define ESPI_S2MW0_STOM_POS		8u
83 #define ESPI_S2MW0_STOM_SRC_POS		8u
88 #define ESPI_S2MW0_STOM_SRC_ESPI_RST	0u
92 #define ESPI_S2MW0_STOM_STATE_POS	12u
95 #define ESPI_S2MW0_CHG0_POS		16u
97 #define ESPI_S2MW0_CHG1_POS		17u
99 #define ESPI_S2MW0_CHG2_POS		18u
101 #define ESPI_S2MW0_CHG3_POS		19u
103 #define ESPI_S2MW0_CHG_ALL_POS		16u
106 /* 0 <= n < 4 */
107 #define ESPI_S2MW1_CHG_POS(n)		((n) + 16u)
112 #define ESPI_S2MW1_OFS			4u
113 #define ESPI_S2MW1_SRC0_POS		0u
115 #define ESPI_S2MW1_SRC1_POS		8u
117 #define ESPI_S2MW1_SRC2_POS		16u
119 #define ESPI_S2MW1_SRC3_POS		24u
121 /* 0 <= n < 4 */
130 #define ESPI_MSVW_IDX_MAX	10u
131 #define ESPI_SMVW_IDX_MAX	10u
133 #define ESPI_NUM_MSVW		11u
134 #define ESPI_NUM_SMVW		11u
141 #define MEC_ESPI_MSVW_NUM_GIRQS     2u
144 #define MSVW_INDEX_OFS		0u
145 #define MSVW_MTOS_OFS		1u
146 #define MSVW_SRC0_ISEL_OFS	4u
147 #define MSVW_SRC1_ISEL_OFS	5u
148 #define MSVW_SRC2_ISEL_OFS	6u
149 #define MSVW_SRC3_ISEL_OFS	7u
150 #define MSVW_SRC0_OFS		8u
151 #define MSVW_SRC1_OFS		9u
152 #define MSVW_SRC2_OFS		10u
153 #define MSVW_SRC3_OFS		11u
156 #define SMVW_INDEX_OFS		0u
157 #define SMVW_STOM_OFS		1u
158 #define SMVW_CHANGED_OFS	2u
159 #define SMVW_SRC0_OFS		4u
160 #define SMVW_SRC1_OFS		5u
161 #define SMVW_SRC2_OFS		6u
162 #define SMVW_SRC3_OFS		7u
166 #define MEC_MSVW_SRC0_IRQ_SEL_POS	0u
167 #define MEC_MSVW_SRC1_IRQ_SEL_POS	8u
168 #define MEC_MSVW_SRC2_IRQ_SEL_POS	16u
169 #define MEC_MSVW_SRC3_IRQ_SEL_POS	24u
193 	((uint32_t)(isel) << ((src) * 8u))
195 #define MEC_MSVW_SRC0_POS	0u
196 #define MEC_MSVW_SRC1_POS	8u
197 #define MEC_MSVW_SRC2_POS	16u
198 #define MEC_MSVW_SRC3_POS	24u
212 	((uint32_t)(val & 0x01u) << ((src) * 8u))
224 	MSVW_SRC0 = 0u,
231 	SMVW_SRC0 = 0u,
248 	VW_RST_SRC_ESPI_RESET = 0u,