Lines Matching +full:4 +full:u

17 #define MCHP_SAF_MAX_FLASH_DEVICES		2U
28 #define MCHP_SAF_FLASH_POLL_INTERVAL		0u
29 #define MCHP_SAF_FLASH_SUS_RSM_INTERVAL		8u
30 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT	2u
31 #define MCHP_SAF_FLASH_SUS_CHK_DELAY		0u
43 #define MCHP_SAF_QMSPI_CLK_DIV			4u
51 #define MCHP_SAF_CS0_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4)
52 #define MCHP_SAF_CS1_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4)
58 #define MCHP_SAF_QMSPI_NUM_FLASH_DESCR		6u
59 #define MCHP_SAF_QMSPI_CS0_START_DESCR		0u
64 #define MCHP_SAF_CM_EXIT_START_DESCR		12u
65 #define MCHP_SAF_CM_EXIT_LAST_DESCR		13u
66 #define MCHP_SAF_POLL_STS_START_DESCR		14u
67 #define MCHP_SAF_POLL_STS_END_DESCR		15u
68 #define MCHP_SAF_NUM_GENERIC_DESCR		4u
146  *	op0 = SPI flash erase 4KB sector opcode
151  *	op0 = SPI flash read 1-4-4 continuous mode opcode
172 #define MCHP_W25Q128_SIZE (16U * 1024U * 1024U)
183 		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
185 /* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
205 		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
230 		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
252 		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
265 #define MCHP_W25Q128_OPD MCHP_SAF_OPCODE_REG_VAL(0xb9u, 0xabu, 0u, 0u)
281 #define MCHP_W25Q128_CONT_MODE_PREFIX_VAL	0u
291 #define MCHP_SAF_PD_EVENT_INTERVAL_25US		1279u
294 #define MCHP_W25Q128_FLAGS			0U
298 #define MCHP_W25Q256_SIZE (32U * 1024U * 1024U)
350 #define MCHP_W25Q256_OPD MCHP_SAF_OPCODE_REG_VAL(0xb9U, 0xabU, 0U, 0U)
354 #define MCHP_W25Q256_CONT_MODE_PREFIX_VAL 0U
356 #define MCHP_W25Q256_FLAGS 0U
360 		MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 2U)
363 		MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 1U)
367 		MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 8U)
370 		MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 7U)
463  * Thread numbers are 4-bit
468  *     2                4h, 5h        Host PCH ME
470  *     4                N/A           Not defined/used
486  * b[20:4] = ProtectionRegions[16:0]
488  * b[20:4] = ProtectionRegions[16:0]
494 #define MCHP_SAF_MSTR_HOST_PCH		0U
495 #define MCHP_SAF_MSTR_HOST_CPU		1U
496 #define MCHP_SAF_MSTR_HOST_PCH_ME	2U
497 #define MCHP_SAF_MSTR_HOST_PCH_LAN	3U
498 #define MCHP_SAF_MSTR_RSVD4		4U
499 #define MCHP_SAF_MSTR_EC		5U
500 #define MCHP_SAF_MSTR_HOST_PCH_IE	6U