Lines Matching +full:4 +full:u

22 #define MCHP_GCFG_DEV_ID_REG32_OFS	28u
32 #define MCHP_GCFG_REV_A1		2u
33 #define MCHP_GCFG_REV_B0		3u
38  * bits[7:4] = chip family
43 #define MCHP_GCFG_SUB_ID_PKG_UNDEF	0u
44 #define MCHP_GCFG_SUB_ID_PKG_64_PIN	1u
45 #define MCHP_GCFG_SUB_ID_PKG_84_PIN	2u
46 #define MCHP_GCFG_SUB_ID_PKG_128_PIN	3u
47 #define MCHP_GCFG_SUB_ID_PKG_144_PIN	4u
48 #define MCHP_GCFG_SUB_ID_PKG_176_PIN	7u
50 #define MCHP_GCFG_SUB_ID_FAM_POS	4u
51 #define MCHP_GCFG_SUB_ID_FAM_MASK	GENMASK(7, 4)
52 #define MCHP_GCFG_SUB_ID_FAM_UNDEF	0u
85 #define MCHP_HOST_CFG_LDN_IDX		7u
94 	volatile uint8_t RSVD1[4];