Lines Matching +full:4 +full:u
12 #define MAX3421E_MAX_EP_SIZE 64U
16 #define MAX3421E_CMD_REG_SHIFT 3U
18 #define MAX3421E_CMD_DIR_RD 0U
30 #define MAX3421E_REG_RCVFIFO 1U
33 #define MAX3421E_REG_SNDFIFO 2U
36 #define MAX3421E_REG_SUDFIFO 4U
39 #define MAX3421E_REG_RCVBC 6U
43 #define MAX3421E_REG_SNDBC 7U
47 #define MAX3421E_REG_USBIRQ 13U
53 #define MAX3421E_REG_USBIEN 14U
59 #define MAX3421E_REG_USBCTL 15U
61 #define MAX3421E_PWRDOWN BIT(4)
64 #define MAX3421E_REG_CPUCTL 16U
70 #define MAX3421E_REG_PINCTL 17U
71 #define MAX3421E_FDUPSPI BIT(4)
78 #define MAX3421E_REG_REVISION 18U
81 #define MAX3421E_REG_IOPINS1 20U
82 #define MAX3421E_REG_IOPINS2 21U
83 #define MAX3421E_REG_GPINIRQ 22U
84 #define MAX3421E_REG_GPINIE 23U
85 #define MAX3421E_REG_GPINPOL 24U
88 #define MAX3421E_REG_HIRQ 25U
89 #define MAX3421E_REG_HIEN 26U
93 #define MAX3421E_SUSDN BIT(4)
100 #define MAX3421E_REG_MODE 27U
104 #define MAX3421E_SEPIRQ BIT(4)
111 #define MAX3421E_REG_PERADDR 28U
115 #define MAX3421E_REG_HCTL 29U
119 #define MAX3421E_RCVTOG0 BIT(4)
126 #define MAX3421E_REG_HXFR 30U
130 #define MAX3421E_SETUP BIT(4)
154 #define MAX3421E_REG_HRSL 31U
159 #define MAX3421E_RCVTOGRD BIT(4)