Lines Matching +full:4 +full:u
13 #define QMPSPI_HW_VER 4u
17 #define MCHP_QMSPI_MAX_DESCR 16u
19 #define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 96000000u
21 ((MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ) / 1000u)
22 #define MCHP_QMSPI_MIN_FREQ_KHZ (MCHP_QMSPI_MAX_FREQ_KHZ / 256u)
25 #define MCHP_QMSPI_SPI_MODE0 0u
34 #define MCHP_QMSPI_TX_DMA_REQ_ID 10u
35 #define MCHP_QMSPI_RX_DMA_REQ_ID 11u
38 #define MCHP_QMSPI_TX_FIFO_LEN 8u
39 #define MCHP_QMSPI_RX_FIFO_LEN 8u
42 #define MCHP_QMSPI_LDMA_RX_CHANNELS 3u
43 #define MCHP_QMSPI_LDMA_TX_CHANNELS 3u
45 #define MCHP_QMSPI_M_ACT_SRST_OFS 0u
46 #define MCHP_QMSPI_M_SPI_MODE_OFS 1u
47 #define MCHP_QMSPI_M_CLK_DIV_OFS 2u
48 #define MCHP_QMSPI_CTRL_OFS 4u
49 #define MCHP_QMSPI_EXE_OFS 8u
60 #define MCHP_QMSPI_DESCR_OFS(n) (0x30u + ((uint32_t)(n) * 4u))
134 #define MCHP_QMSPI_M_LDMA_TX_EN BIT(4)
135 #define MCHP_QMSPI_M_CPOL_POS 8u
139 #define MCHP_QMSPI_M_CPHA_MOSI_POS 9u
141 #define MCHP_QMSPI_M_CPHA_MOSI_CE1 0u
145 #define MCHP_QMSPI_M_CPHA_MIS0_POS 10u
147 #define MCHP_QMSPI_M_CPHA_MISO_CE1 0u
151 #define MCHP_QMSPI_M_SIG_POS 8u
154 #define MCHP_QMSPI_M_SIG_MODE0_VAL 0u
158 #define MCHP_QMSPI_M_SIG_MODE0 0u
159 #define MCHP_QMSPI_M_SIG_MODE1 SHLU32(6u, MCHP_QMSPI_M_SIG_POS)
160 #define MCHP_QMSPI_M_SIG_MODE2 SHLU32(1u, MCHP_QMSPI_M_SIG_POS)
161 #define MCHP_QMSPI_M_SIG_MODE3 SHLU32(7u, MCHP_QMSPI_M_SIG_POS)
162 #define MCHP_QMSPI_M_CS_POS 12u
164 #define MCHP_QMSPI_M_CS_MASK SHLU32(3u, 12)
165 #define MCHP_QMSPI_M_CS0 SHLU32(0u, 12)
166 #define MCHP_QMSPI_M_CS1 SHLU32(1u, 12)
170 #define MCHP_QMSPI_M_FDIV_POS 16u
176 #define MCHP_QMSPI_C_IFM_1X 0u
177 #define MCHP_QMSPI_C_IFM_2X 1u
178 #define MCHP_QMSPI_C_IFM_4X 2u
179 #define MCHP_QMSPI_C_TX_POS 2u
180 #define MCHP_QMSPI_C_TX_MASK SHLU32(3u, MCHP_QMSPI_C_TX_POS)
181 #define MCHP_QMSPI_C_TX_DIS 0u
182 #define MCHP_QMSPI_C_TX_DATA SHLU32(1u, MCHP_QMSPI_C_TX_POS)
183 #define MCHP_QMSPI_C_TX_ZEROS SHLU32(2u, MCHP_QMSPI_C_TX_POS)
184 #define MCHP_QMSPI_C_TX_ONES SHLU32(3u, MCHP_QMSPI_C_TX_POS)
185 #define MCHP_QMSPI_C_TX_DMA_POS 4u
186 #define MCHP_QMSPI_C_TX_DMA_MASK SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS)
187 #define MCHP_QMSPI_C_TX_DMA_DIS 0u
188 #define MCHP_QMSPI_C_TX_DMA_1B SHLU32(1u, MCHP_QMSPI_C_TX_DMA_POS)
189 #define MCHP_QMSPI_C_TX_DMA_2B SHLU32(2u, MCHP_QMSPI_C_TX_DMA_POS)
190 #define MCHP_QMSPI_C_TX_DMA_4B SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS)
191 #define MCHP_QMSPI_C_TX_LDMA_CH0 SHLU32(1u, MCHP_QMSPI_C_TX_DMA_POS)
192 #define MCHP_QMSPI_C_TX_LDMA_CH1 SHLU32(2u, MCHP_QMSPI_C_TX_DMA_POS)
193 #define MCHP_QMSPI_C_TX_LDMA_CH2 SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS)
194 #define MCHP_QMSPI_C_RX_POS 6u
195 #define MCHP_QMSPI_C_RX_DIS 0u
197 #define MCHP_QMSPI_C_RX_DMA_POS 7u
198 #define MCHP_QMSPI_C_RX_DMA_MASK SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS)
199 #define MCHP_QMSPI_C_RX_DMA_DIS 0u
200 #define MCHP_QMSPI_C_RX_DMA_1B SHLU32(1u, MCHP_QMSPI_C_RX_DMA_POS)
201 #define MCHP_QMSPI_C_RX_DMA_2B SHLU32(2u, MCHP_QMSPI_C_RX_DMA_POS)
202 #define MCHP_QMSPI_C_RX_DMA_4B SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS)
203 #define MCHP_QMSPI_C_RX_LDMA_CH0 SHLU32(1u, MCHP_QMSPI_C_RX_DMA_POS)
204 #define MCHP_QMSPI_C_RX_LDMA_CH1 SHLU32(2u, MCHP_QMSPI_C_RX_DMA_POS)
205 #define MCHP_QMSPI_C_RX_lDMA_CH2 SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS)
207 #define MCHP_QMSPI_C_CLOSE_POS 9u
208 #define MCHP_QMSPI_C_NO_CLOSE 0u
210 #define MCHP_QMSPI_C_XFR_UNITS_POS 10u
211 #define MCHP_QMSPI_C_XFR_UNITS_MASK SHLU32(3u, MCHP_QMSPI_C_XFR_UNITS_POS)
212 #define MCHP_QMSPI_C_XFR_UNITS_BITS 0u
213 #define MCHP_QMSPI_C_XFR_UNITS_1 SHLU32(1u, MCHP_QMSPI_C_XFR_UNITS_POS)
214 #define MCHP_QMSPI_C_XFR_UNITS_4 SHLU32(2u, MCHP_QMSPI_C_XFR_UNITS_POS)
215 #define MCHP_QMSPI_C_XFR_UNITS_16 SHLU32(3u, MCHP_QMSPI_C_XFR_UNITS_POS)
216 #define MCHP_QMSPI_C_NEXT_DESCR_POS 12u
219 #define MCHP_QMSPI_C_DESCR0 0u
231 #define MCHP_QMSPI_C_DESCR_EN_POS 16u
237 #define MCHP_QMSPI_C_XFR_NUNITS_POS 17u
249 #define MCHP_QMSPI_IFC_DFLT 0u
254 #define MCHP_QMSPI_IFC_PD_ON_NS BIT(4)
267 #define MCHP_QMSPI_STS_PROG_ERR BIT(4)
279 #define MCHP_QMSPI_STS_CD_POS 24u
284 #define MCHP_QMSPI_TX_BUF_CNT_STS_POS 0u
286 #define MCHP_QMSPI_RX_BUF_CNT_STS_POS 16u
294 #define MCHP_QMSPI_IEN_PROG_ERR BIT(4)
305 #define MCHP_QMSPI_TX_BUF_CNT_TRIG_POS 0u
306 #define MCHP_QMSPI_RX_BUF_CNT_TRIG_POS 16u
311 #define MCHP_QMSPI_DLY_CS_ON_CK_STR_POS 0u
313 #define MCHP_QMSPI_DLY_CK_STP_CS_OFF_POS 8u
315 #define MCHP_QMSPI_DLY_LST_DAT_HLD_POS 16u
317 #define MCHP_QMSPI_DLY_CS_OFF_CS_ON_POS 24u
326 #define MCHP_QMSPI_ACTRL_CS_POS 4
327 #define MCHP_QMSPI_ACTRL_CS0 0u
331 #define MCHP_QMSPI_ACTRL_DBP_0 0u
368 /* Each Local DMA channel implements 4 32-bit registers.
386 /* LDMA unit(access) size: 1, 2, or 4 bytes */
387 #define MCHP_QMSPI_LDC_ASZ_POS 4
389 #define MCHP_QMSPI_LDC_ASZ_1 0u