Lines Matching +full:4 +full:u

18 #define MCHP_SAF_MAX_FLASH_DEVICES 2U
29 #define MCHP_SAF_FLASH_POLL_INTERVAL 0U
30 #define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8U
31 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2U
32 #define MCHP_SAF_FLASH_SUS_CHK_DELAY 0U
43 #define MCHP_SAF_QMSPI_CLK_DIV 2U
48 #define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6U
49 #define MCHP_SAF_QMSPI_CS0_START_DESCR 0U
54 #define MCHP_SAF_CM_EXIT_START_DESCR  12U
55 #define MCHP_SAF_CM_EXIT_LAST_DESCR   13U
56 #define MCHP_SAF_POLL_STS_START_DESCR 14U
57 #define MCHP_SAF_POLL_STS_END_DESCR   15U
58 #define MCHP_SAF_NUM_GENERIC_DESCR    4U
122  *	op0 = SPI flash erase 4KB sector opcode
127  *	op0 = SPI flash read 1-4-4 continuous mode opcode
147 #define MCHP_W25Q128_SIZE (16U * 1024U * 1024U)
158 		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
160 /* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
187 		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
213 #define MCHP_W25Q128_CONT_MODE_PREFIX_VAL 0U
215 #define MCHP_W25Q128_FLAGS 0U
219 #define MCHP_W25Q256_SIZE (32U * 1024U * 1024U)
274 #define MCHP_W25Q256_CONT_MODE_PREFIX_VAL 0U
276 #define MCHP_W25Q256_FLAGS 0U
280 		MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 2U)
284 		MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 8U)
354  * Thread numbers are 4-bit
359  *     2                4h, 5h        Host PCH ME
361  *     4                N/A           Not defined/used
377  * b[20:4] = ProtectionRegions[16:0]
379  * b[20:4] = ProtectionRegions[16:0]
385 #define MCHP_SAF_MSTR_HOST_PCH		0U
386 #define MCHP_SAF_MSTR_HOST_CPU		1U
387 #define MCHP_SAF_MSTR_HOST_PCH_ME	2U
388 #define MCHP_SAF_MSTR_HOST_PCH_LAN	3U
389 #define MCHP_SAF_MSTR_RSVD4		4U
390 #define MCHP_SAF_MSTR_EC		5U
391 #define MCHP_SAF_MSTR_HOST_PCH_IE	6U