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/Zephyr-latest/dts/bindings/gpio/
Dti,boosterpack-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
15 through 40. The BoosterPack pinout is depicted below:
17 1 3.3V 21 5V 40 GPIO 20 GND
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
Dnxp,parallel-lcd-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,parallel-lcd-connector"
9 exposed on a 40 pin flexible printed cable connector. The pins have the
12 FPC Pin Function
17 5-7 GND
18 8-12 LCD D11-D15
19 13-14 GND
20 15-20 LCD D5-D10
21 21-23 GND
22 24-28 LCD D0-D4
[all …]
Draspberrypi-40pins-header.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on Raspberry Pi 40-pin header.
11 - 3V3 5V -
12 0 GPIO2/I2C1_SDA 5V -
13 1 GPIO3/I2C1_SCL GND -
15 - GND GPIO15/UART0_RXD 4
17 7 GPIO27 GND -
19 - 3V3 GPIO24 10
20 11 GPIO10/SPI0_MOSI GND -
23 - GND GPIO7/SPI0_CE1 16
[all …]
Dsparkfun,micromod-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
33 - 04 -> I2C_INT# PIN 16
[all …]
Dnxp,cam-44pins-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on NXP 44-pin board-to-board camera connector.
28 40 DGND DGND 39
31 compatible: "nxp,cam-44pins-connector"
33 include: [gpio-nexus.yaml, base.yaml]
Drichtek,rt1718s.yaml2 # SPDX-License-Identifier: Apache-2.0
9 address. Feature-specific(GPIO, TCPC) properties should be placed in a child
14 rt1718s_port0: rt1718s@40 {
17 irq-gpios = <&gpioe 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
20 compatible = "richtek,rt1718s-gpio-port";
22 gpio-controller;
23 #gpio-cells = <2>;
31 include: [i2c-device.yaml]
34 irq-gpios:
35 type: phandle-array
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx8m-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "40-ohm";
16 slew-rate = "slow";
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1
28 drive-open-drain: ODE=1
29 slew-rate: SRE=<enum_idx>
30 drive-strength: DSE=<enum_idx>
31 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
33 If only required properties are supplied, the pin will have the following
[all …]
Dambiq,apollo3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Ambiq Apollo3 pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a UART0 TX
7 to pin 60 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
33 input-enable;
38 The 'uart0_default' child node encodes the pin configurations for a
[all …]
Dambiq,apollo4-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Ambiq Apollo4 pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a UART0 TX
7 to pin 60 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
33 input-enable;
38 The 'uart0_default' child node encodes the pin configurations for a
[all …]
/Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/
Dup_squared.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * This uses pin 40 on HAT as LED, and pin 38 as interrupt line.
12 * () Advanced -> HAT Configurations:
13 * - HD-Audio / I2S6 Selec -> Disabled
15 * - GPIO 27 (Pin38) Confi -> Input
16 * - GPIO 28 (Pin40) Confi -> Output
21 compatible = "test-gpio-basic-api";
23 out-gpios = <&gpio_w 19 0>; /* HAT Pin 40 */
24 in-gpios = <&gpio_w 18 0>; /* HAT Pin 38 */
/Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/boards/
Dup_squared.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * This uses pin 40 on HAT as LED.
12 * () Advanced -> HAT Configurations:
13 * - HD-Audio / I2S6 Selec -> Disabled
15 * - GPIO 28 (Pin40) Confi -> Output
24 compatible = "gpio-leds";
27 label = "HAT Pin 40 as LED";
/Zephyr-latest/dts/bindings/w1/
Dadi,max32-w1.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
4 description: ADI MAX32xxx MCUs 1-Wire Master
6 include: [w1-master.yaml, pinctrl-device.yaml]
8 compatible: "adi,max32-w1"
20 pinctrl-0:
23 pinctrl-names:
26 internal-pullup:
32 0 - Internal pullup disabled.
33 1 - Internal pullup enabled.
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
148 #define MIO40 40
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
180 #define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
202 #define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
237 #define MIO_GROUP_CAN1_8_GRP_PINS 40, 41
260 #define MIO_GROUP_UART1_8_GRP_PINS 40, 41
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra-common.h4 * SPDX-License-Identifier: Apache-2.0
25 #define RA_PINCFG(port, pin, psel, opt) \ argument
26 ((((psel)&PSEL_MASK) << PSEL_POS) | (((pin)&PIN_MASK) << PIN_POS) | \
30 #if RA_SOC_PINS >= 40
31 #define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
35 #define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
39 #define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
43 #define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
/Zephyr-latest/dts/bindings/sensor/
Dvishay,vcnl4040.yaml2 # SPDX-License-Identifier: Apache-2.0
10 include: [sensor-device.yaml, i2c-device.yaml]
13 int-gpios:
14 type: phandle-array
16 The INT pin signals that a programmable interrupt function
18 triggered. The sensor generates an active-low level signal
21 led-current:
27 - 50
28 - 75
29 - 100
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_ti_cc32xx.c3 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
15 /* pin to pad mapping (255 indicates invalid pin) */
18 21U, 22U, 23U, 24U, 40U, 28U, 29U, 25U, 255U, 255U, 255U, 255U, 255U,
26 uint8_t pin; in pinctrl_configure_pin() local
28 pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK; in pinctrl_configure_pin()
29 if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) { in pinctrl_configure_pin()
30 return -EINVAL; in pinctrl_configure_pin()
33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U)); in pinctrl_configure_pin()
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dsi32-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
65 #define SI32_SIGNAL_UART0_TX 40
108 * @param pin Port pin number (0 to 15)
110 #define SI32_MUX(fun, port, pin) \ argument
111 ((((port)&0x7)) | (((pin)&0xF) << 3) | ((SI32_SIGNAL_##fun & 0x7F) << 22))
Dsmartbond-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 /** Definitions of pin functions */
51 #define SMARTBOND_FUNC_PORT3_DCF 40
76 #define SMARTBOND_PINMUX(func, port, pin) \ argument
79 (pin) << SMARTBOND_PINMUX_PIN_POS)
/Zephyr-latest/soc/espressif/common/
DKconfig.spiram2 # SPDX-License-Identifier: Apache-2.0
7 bool "Support for external, SPI-connected RAM"
58 bool "ESP-PSRAM16 or APS1604"
62 bool "ESP-PSRAM32 or IS25WP032"
66 bool "ESP-PSRAM64, LY68L6400 or APS6408"
95 bool "40MHz clock speed"
111 default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M
134 bool "Move Read-Only Data in Flash to PSRAM"
148 Enable MSPI Error-Correcting Code function when accessing SPIRAM.
149 If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
[all …]
/Zephyr-latest/dts/bindings/can/
Dmicrochip,mcp251xfd.yaml2 # SPDX-License-Identifier: Apache-2.0
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30 osc-freq:
35 int-gpios:
36 type: phandle-array
39 The interrupt signal from the controller is active low in push-pull mode.
[all …]
/Zephyr-latest/boards/renesas/ek_ra4e2/doc/
Dindex.rst9 The RA4E2 Group delivers up to 100 MHz of CPU performance using an Arm® Cortex®-M33 core
10 with 128 KB of code flash memory, 4 KB of data flash memory, and 40 KB of SRAM. RA4E2 MCUs
11 offer high-performance and optimized peripheral functions along with the smallest package
12 options, including space-saving 36-pin BGA and 32-pin QFN packages. The RA4E2
15 The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
18 **MCU Native Pin Access**
19 - R7FA4E2B93CFM MCU (referred to as RA MCU)
20 - 100 MHz, Arm® Cortex®-M33 core
21 - 128 kB Code Flash, 40 kB SRAM
22 - 64 pins, LQFP package
[all …]
/Zephyr-latest/boards/shields/g1120b0mipi/doc/
Dindex.rst10 1-lane MIPI interface. This display connects to the i.MX RT595 Evaluation Kit.
16 This display uses a 40 pin FPC interface, which is available on many
22 +-----------------------+------------------------+
23 | FPC Connector Pin | Function |
26 +-----------------------+------------------------+
28 +-----------------------+------------------------+
30 +-----------------------+------------------------+
32 +-----------------------+------------------------+
34 +-----------------------+------------------------+
36 +-----------------------+------------------------+
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4m/doc/
Dindex.rst16 This display uses a 40 pin FPC interface, which is available on many
22 +-----------------------+------------------------+
23 | FPC Connector Pin | Function |
26 +-----------------------+------------------------+
28 +-----------------------+------------------------+
30 +-----------------------+------------------------+
32 +-----------------------+------------------------+
34 +-----------------------+------------------------+
36 +-----------------------+------------------------+
38 +-----------------------+------------------------+
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4ma0/doc/
Dindex.rst16 This display uses a 40 pin FPC interface, which is available on many
22 +-----------------------+------------------------+
23 | FPC Connector Pin | Function |
26 +-----------------------+------------------------+
28 +-----------------------+------------------------+
30 +-----------------------+------------------------+
32 +-----------------------+------------------------+
34 +-----------------------+------------------------+
36 +-----------------------+------------------------+
38 +-----------------------+------------------------+
[all …]
/Zephyr-latest/drivers/sensor/adi/adt7420/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
12 Enable the driver for Analog Devices ADT7420 High-Accuracy
13 16-bit Digital I2C Temperature Sensors.
27 range -40 150
30 The critical overtemperature pin asserts when the temperature
46 depends on $(dt_compat_any_has_prop,$(DT_COMPAT_ADI_ADT7420),int-gpios)
52 depends on $(dt_compat_any_has_prop,$(DT_COMPAT_ADI_ADT7420),int-gpios)

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