1# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  The Ambiq Apollo3 pin controller is a node responsible for controlling
6  pin function selection and pin properties, such as routing a UART0 TX
7  to pin 60 and enabling the pullup resistor on that pin.
8
9  The node has the 'pinctrl' node label set in your SoC's devicetree,
10  so you can modify it like this:
11
12  &pinctrl {
13    /* your modifications go here */
14  };
15
16  All device pin configurations should be placed in child nodes of the
17  'pinctrl' node, as shown in this example:
18
19  /* You can put this in places like a board-pinctrl.dtsi file in
20   * your board directory, or a devicetree overlay in your application.
21  */
22
23  /* include pre-defined combinations for the SoC variant used by the board */
24  #include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
25
26  &pinctrl {
27    uart0_default: uart0_default {
28      group1 {
29        pinmux = <UART0TX_P60>;
30      };
31      group2 {
32        pinmux = <UART0RX_P47>;
33        input-enable;
34      };
35    };
36  };
37
38  The 'uart0_default' child node encodes the pin configurations for a
39  particular state of a device; in this case, the default (that is, active)
40  state.
41
42  As shown, pin configurations are organized in groups within each child node.
43  Each group can specify a list of pin function selections in the 'pinmux'
44  property.
45
46  A group can also specify shared pin properties common to all the specified
47  pins, such as the 'input-enable' property in group 2.
48
49compatible: "ambiq,apollo3-pinctrl"
50
51include: base.yaml
52
53child-binding:
54  description: |
55    Definitions for a pinctrl state.
56  child-binding:
57
58    include:
59      - name: pincfg-node.yaml
60        property-allowlist:
61          - input-enable
62          - drive-push-pull
63          - drive-open-drain
64          - bias-high-impedance
65          - bias-pull-up
66          - bias-pull-down
67
68    properties:
69      pinmux:
70        required: true
71        type: array
72        description: |
73          An array of pins sharing the same group properties. Each
74          element of the array is an integer constructed from the
75          pin number and the alternative function of the pin.
76      drive-strength:
77        type: string
78        enum:
79          - "0.1"
80          - "0.5"
81          - "0.75"
82          - "1.0"
83        default: "0.1"
84        description: |
85          The drive strength of a pin, relative to full-driver strength.
86          The default value is 0.1, which is the reset value of resigers
87          PADREGx.PADnSTRNG and ALTPADCFGx.PADn_DS1.
88      ambiq,pull-up-ohms:
89        type: int
90        enum:
91          - 1500
92          - 6000
93          - 12000
94          - 24000
95        default: 1500
96        description: |
97          The 1.5K-24K pullup values are valid for select I2C enabled pads.
98          For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49.
99          The default value is 1500 ohms, which is the reset value of
100          register PADREGx.PADxRSEL.
101      ambiq,iom-nce-module:
102        type: int
103        default: 0
104        description: |
105          IOM nCE module select, selects the SPI channel (CE) number (0-3).
106          The default value is 0, which is the reset value of
107          register CFGx.GPIOnOUTCFG. If the pin is not a CE, this
108          descriptor will be ignored.
109      ambiq,iom-mspi:
110        type: int
111        default: 0
112        description: |
113          Indicates the module which uses specific CE pin, 1 if CE is IOM, 0 if MSPI.
114          User should check g_ui8NCEtable in am_hal_gpio.c for the mapping
115          information and config the pins accordingly, we give a default value
116          0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in
117          ambiq hal. If the pin is not a CE, this descriptor will be ignored.
118      ambiq,iom-num:
119        type: int
120        default: 0
121        description: |
122          Indicates the instance which uses specific CE pin.
123          IOM number (0-5) or MSPI (0-2).
124          User should check g_ui8NCEtable in am_hal_gpio.c for the mapping
125          information and config the pins accordingly, we give a default value
126          0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in
127          ambiq hal. If the pin is not a CE, this descriptor will be ignored.
128