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/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi19 nxp,speed = "100-mhz";
28 nxp,speed = "50-mhz";
43 nxp,speed = "200-mhz";
50 nxp,speed = "200-mhz";
58 nxp,speed = "50-mhz";
68 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
88 nxp,speed = "100-mhz";
99 nxp,speed = "200-mhz";
109 nxp,speed = "200-mhz";
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/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
59 nxp,speed = "50-mhz";
74 nxp,speed = "200-mhz";
88 nxp,speed = "200-mhz";
98 nxp,speed = "100-mhz";
109 nxp,speed = "100-mhz";
121 nxp,speed = "100-mhz";
133 nxp,speed = "100-mhz";
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/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
59 nxp,speed = "50-mhz";
74 nxp,speed = "200-mhz";
88 nxp,speed = "200-mhz";
98 nxp,speed = "100-mhz";
109 nxp,speed = "100-mhz";
119 nxp,speed = "100-mhz";
131 nxp,speed = "100-mhz";
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/Zephyr-latest/dts/bindings/clock/
Dst,stm32u5-msi-clock.yaml22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
Dst,stm32-msi-clock.yaml19 - 1 # range 1 around 200 kHz
23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
29 nxp,speed = "50-mhz";
43 nxp,speed = "200-mhz";
49 nxp,speed = "100-mhz";
61 nxp,speed = "200-mhz";
69 nxp,speed = "100-mhz";
77 nxp,speed = "100-mhz";
91 nxp,speed = "100-mhz";
103 nxp,speed = "100-mhz";
115 nxp,speed = "100-mhz";
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/Zephyr-latest/boards/nxp/mimxrt1064_evk/
Dmimxrt1064_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
59 nxp,speed = "50-mhz";
74 nxp,speed = "200-mhz";
88 nxp,speed = "200-mhz";
98 nxp,speed = "100-mhz";
109 nxp,speed = "100-mhz";
119 nxp,speed = "100-mhz";
129 nxp,speed = "100-mhz";
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/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
30 nxp,speed = "50-mhz";
44 nxp,speed = "200-mhz";
50 nxp,speed = "100-mhz";
62 nxp,speed = "200-mhz";
70 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
92 nxp,speed = "100-mhz";
104 nxp,speed = "100-mhz";
116 nxp,speed = "100-mhz";
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/Zephyr-latest/boards/madmachine/mm_feather/
Dmm_feather-pinctrl.dtsi19 nxp,speed = "100-mhz";
31 nxp,speed = "100-mhz";
41 nxp,speed = "100-mhz";
52 nxp,speed = "100-mhz";
58 nxp,speed = "100-mhz";
69 nxp,speed = "100-mhz";
83 nxp,speed = "100-mhz";
92 nxp,speed = "100-mhz";
98 nxp,speed = "100-mhz";
102 /* fast pinmux settings for USDHC (over 100 Mhz) */
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/Zephyr-latest/boards/madmachine/mm_swiftio/
Dmm_swiftio-pinctrl.dtsi28 nxp,speed = "100-mhz";
39 nxp,speed = "100-mhz";
51 nxp,speed = "100-mhz";
61 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
89 nxp,speed = "100-mhz";
103 nxp,speed = "100-mhz";
112 nxp,speed = "100-mhz";
118 nxp,speed = "100-mhz";
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/Zephyr-latest/drivers/memc/
Dmemc_mcux_flexspi_aps6408l.c47 #define APS_6408L_RLC_200 0x10 /* 200MHz input clock read latency */
61 #define APS_6408L_WLC_200 0x20 /* 200MHz input clock write latency */
252 /* Set read latency code and type for 200MHz flash clock operation */ in memc_flexspi_aps6408l_init()
256 LOG_ERR("Could not set 200MHz read latency code"); in memc_flexspi_aps6408l_init()
259 /* Set write latency code and type for 200MHz flash clock operation */ in memc_flexspi_aps6408l_init()
262 LOG_ERR("Could not set 200MHz write latency code"); in memc_flexspi_aps6408l_init()
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
DKconfig.soc20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
36 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi20 nxp,speed = "100-mhz";
35 nxp,speed = "200-mhz";
49 nxp,speed = "200-mhz";
60 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
84 nxp,speed = "100-mhz";
97 nxp,speed = "100-mhz";
110 nxp,speed = "100-mhz";
123 nxp,speed = "100-mhz";
137 nxp,speed = "100-mhz";
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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mcux-rt-pinctrl.yaml17 nxp,speed = "100-mhz";
22 slow slew rate, and 100 MHZ speed.
142 - "50-mhz"
143 - "100-mhz"
144 - "150-mhz"
145 - "200-mhz"
148 00 SPEED_0_low_50MHz_ — low(50MHz)
149 01 SPEED_1_medium_100MHz_ — medium(100MHz)
150 10 SPEED_2_medium_150MHz_ — medium(150MHz)
151 11 SPEED_3_max_200MHz_ — max(200MHz)
Dnxp,s32ze-pinctrl.yaml102 0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V)
103 4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V)
104 5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V)
105 6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V)
106 7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
108 0: FMAX_18 = 208 MHz
109 4: FMAX_18 = 150 MHz
110 5: FMAX_18 = 133 MHz
111 6: FMAX_18 = 100 MHz
112 7: FMAX_18 = 50 MHz
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Dgd,gd32-pinctrl-af.yaml73 signal (default: 2MHz).
101 default: "max-speed-2mhz"
103 - "max-speed-2mhz"
104 - "max-speed-25mhz"
105 - "max-speed-50mhz"
106 - "max-speed-200mhz"
109 slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
Dnxp,imx8m-pinctrl.yaml105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
/Zephyr-latest/tests/drivers/pinctrl/gd32/boards/
Dgd32f450i_eval.overlay45 slew-rate = "max-speed-2mhz";
49 slew-rate = "max-speed-25mhz";
53 slew-rate = "max-speed-50mhz";
57 slew-rate = "max-speed-200mhz";
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
DKconfig.soc20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
36 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
/Zephyr-latest/boards/renesas/fpb_ra6e2/doc/
Dindex.rst10 the 200 MHz Arm® Cortex®-M33 core with TrustZone, enables users to
20 - 200MHz Arm Cortex-M33 based RA6E2 MCU in 64 pins, LQFP package
25 providing precision 24.000 MHz and 32,768 Hz reference clock.
135 * Target Interface Speed: 4 MHz
151 …ducts/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e2-entry-line-200mhz-arm-cortex-m33-gen…
/Zephyr-latest/boards/nuvoton/numaker_pfm_m467/doc/
Dindex.rst13 - Core clock up to 200 MHz
30 * The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 200MHz.
/Zephyr-latest/boards/renesas/ek_ra6m4/doc/
Dindex.rst15 active power consumption down to 99uA/MHz running the CoreMark®
22 - 200MHz Arm Cortex-M33 based RA6M4 MCU in 144 pins, LQFP package
26 providing precision 24.000 MHz and 32,768 Hz reference clock.
153 * Target Interface Speed: 4 MHz
169 …m/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m4-200mhz-arm-cortex-m33-tru…
/Zephyr-latest/boards/renesas/fpb_ra6e1/doc/
Dindex.rst12 with 790.75 CoreMark, which are 3.95CoreMark / Mhz.
18 - 200MHz Arm Cortex-M33 based RA6E1 MCU in 100 pins, LQFP package
23 precision 24.000 MHz (not fitted) and 32,768 Hz reference clocks are also available
135 * Target Interface Speed: 4 MHz
151 …m/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6e1-200mhz-arm-cortex-m33-ent…
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
[all …]
/Zephyr-latest/boards/aspeed/ast1030_evb/doc/
Dindex.rst54 The AST1030 SOC is configured to use external 25MHz clock input to generate 200Mhz system clock by

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