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/Zephyr-latest/drivers/flash/
Dflash_cadence_qspi_nor_ll.h14 #define CAD_INVALID -1
18 #define CAD_QSPI_ADDR_FASTREAD_DUAL_IO 1
21 #define CAT_QSPI_ADDR_DUAL_IO 1
24 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) argument
31 #define CAD_QSPI_CFG_BAUDDIV(x) FIELD_PREP(0x780000, x) argument
33 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) argument
41 #define CAD_QSPI_DELAY_CSSOT(x) (FIELD_GET(0xff, (x)) << 0) argument
42 #define CAD_QSPI_DELAY_CSEOT(x) (FIELD_GET(0xff, (x)) << 8) argument
43 #define CAD_QSPI_DELAY_CSDADS(x) (FIELD_GET(0xff, (x)) << 16) argument
44 #define CAD_QSPI_DELAY_CSDA(x) (FIELD_GET(0xff, (x)) << 24) argument
[all …]
Dflash_cadence_nand_ll.h18 #define CNF_GET_INIT_COMP(x) (FIELD_GET(BIT(9), x)) argument
19 #define CNF_GET_INIT_FAIL(x) (FIELD_GET(BIT(10), x)) argument
20 #define CNF_GET_CTRL_BUSY(x) (FIELD_GET(BIT(8), x)) argument
21 #define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x)) argument
22 #define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x)) argument
23 #define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x)) argument
24 #define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x)) argument
25 #define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x)) argument
28 #define CNF_GET_NLUNS(x) (FIELD_GET(GENMASK(7, 0), x)) argument
29 #define CNF_GET_DEV_TYPE(x) (FIELD_GET(GENMASK(31, 30), x)) argument
[all …]
/Zephyr-latest/tests/kernel/common/src/
Dprintk.c69 "68719476735 -1 18446744073709551615 ffffffffffffffff\n"
71 "-1 -1 4294967295 ffffffff\n"
75 "0x1 0x 1 0x 1 0x 1\n"
82 "68719476735 -1 18446744073709551615 ffffffffffffffff\n"
84 "-1 -1 4294967295 ffffffff\n"
102 "0x1 0x 1 0x 1 0x 1\n"
109 "68719476735 -1 18446744073709551615 ffffffffffffffff\n"
118 "0x1 0x 1 0x 1 0x 1\n"
124 "68719476735 -1 18446744073709551615 ffffffffffffffff\n"
131 "0x1 0x 1 0x 1 0x 1\n"
[all …]
/Zephyr-latest/samples/subsys/zbus/msg_subscriber/
DREADME.rst31 [0/1] To exit from QEMU enter: 'CTRL+a, x'[QEMU] CPU: qemu32,+nx,+pae
35 I: From listener foo_lis -> Acc x=1, y=10, z=100
36 I: From msg subscriber bar_msg_sub1 -> Acc x=1, y=10, z=100
37 I: From msg subscriber bar_msg_sub2 -> Acc x=1, y=10, z=100
38 I: From msg subscriber bar_msg_sub3 -> Acc x=1, y=10, z=100
39 I: From msg subscriber bar_msg_sub4 -> Acc x=1, y=10, z=100
40 I: From msg subscriber bar_msg_sub5 -> Acc x=1, y=10, z=100
41 I: From msg subscriber bar_msg_sub6 -> Acc x=1, y=10, z=100
42 I: From msg subscriber bar_msg_sub7 -> Acc x=1, y=10, z=100
43 I: From msg subscriber bar_msg_sub8 -> Acc x=1, y=10, z=100
[all …]
Dsample.yaml13 - "^.*?I: AL Memory allocated \\d{1,3} bytes. Total allocated \\d{1,3} bytes$"
14 - "^.*?I: FR Memory freed \\d{1,3} bytes. Total allocated 0 bytes$"
16 - "^.*?D: 1 -> bar_msg_sub1"
34 - "^.*?I: From listener foo_lis -> Acc x=1, y=10, z=100"
35 - "^.*?I: From msg subscriber bar_msg_sub1 -> Acc x=1, y=10, z=100"
36 - "^.*?I: From msg subscriber bar_msg_sub2 -> Acc x=1, y=10, z=100"
37 - "^.*?I: From msg subscriber bar_msg_sub3 -> Acc x=1, y=10, z=100"
38 - "^.*?I: From msg subscriber bar_msg_sub4 -> Acc x=1, y=10, z=100"
39 - "^.*?I: From msg subscriber bar_msg_sub5 -> Acc x=1, y=10, z=100"
40 - "^.*?I: From msg subscriber bar_msg_sub6 -> Acc x=1, y=10, z=100"
[all …]
/Zephyr-latest/lib/libc/minimal/include/
Dstdint.h22 #define INT8_MIN (-INT8_MAX - 1)
23 #define INT16_MIN (-INT16_MAX - 1)
24 #define INT32_MIN (-INT32_MAX - 1)
25 #define INT64_MIN (-INT64_MAX - 1LL)
38 #define INT_FAST8_MIN (-INT_FAST8_MAX - 1)
39 #define INT_FAST16_MIN (-INT_FAST16_MAX - 1)
40 #define INT_FAST32_MIN (-INT_FAST32_MAX - 1)
41 #define INT_FAST64_MIN (-INT_FAST64_MAX - 1LL)
53 #define INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)
54 #define INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v1.h30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
31 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
34 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
46 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
52 #define SSCR1_TIE BIT(1)
58 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
60 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
79 #define SSCR2_TURM1 BIT(1)
[all …]
Dssp_regs_v2.h31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
32 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
35 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
47 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
53 #define SSCR1_TIE BIT(1)
59 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
61 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
80 #define SSCR2_TURM1 BIT(1)
[all …]
Dssp_regs_v3.h32 #define PCMSyCM_OFFSET(x) 0x16 + 0x4*(x) argument
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
39 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
42 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
54 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
63 #define SSCR1_TIE BIT(1)
79 #define SSCR2_TURM1 BIT(1)
96 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
[all …]
/Zephyr-latest/samples/philosophers/src/
Dphil_obj_abstract.h45 K_SEM_DEFINE(fork0, 1, 1);
46 K_SEM_DEFINE(fork1, 1, 1);
47 K_SEM_DEFINE(fork2, 1, 1);
48 K_SEM_DEFINE(fork3, 1, 1);
49 K_SEM_DEFINE(fork4, 1, 1);
50 K_SEM_DEFINE(fork5, 1, 1);
53 #define fork_init(x) k_sem_init(x, 1, 1) argument
55 #define take(x) k_sem_take(x, K_FOREVER) argument
56 #define drop(x) k_sem_give(x) argument
69 #define fork_init(x) k_mutex_init(x) argument
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_max14916.h11 #define MAX14906_ENABLE 1
36 #define MAX149x6_ADDR_MASK GENMASK(4, 1)
40 #define MAX149x6_DOI_LEVEL_MASK(x) BIT(x) argument
43 #define MAX14906_HIGHO_MASK(x) BIT(x) argument
45 #define MAX14906_DO_MASK(x) (GENMASK(1, 0) << (2 * (x))) argument
46 #define MAX14906_CH_DIR_MASK(x) BIT((x) + 4) argument
47 #define MAX14906_CH(x) (x) argument
49 #define MAX14906_CL_MASK(x) (GENMASK(1, 0) << (2 * (x))) argument
52 #define MAX14906_SLED_MASK BIT(1)
55 #define MAX14906_CHAN_MASK_LSB(x) BIT(x) argument
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dprci.h33 #define PLL_R(x) (((x) & 0x3f) << 0) argument
34 #define PLL_F(x) (((x) & 0x1ff) << 6) argument
35 #define PLL_Q(x) (((x) & 0x7) << 15) argument
36 #define PLL_RANGE(x) (((x) & 0x7) << 18) argument
37 #define PLL_BYPASS(x) (((x) & 0x1) << 24) argument
38 #define PLL_FSE(x) (((x) & 0x1) << 25) argument
39 #define PLL_LOCK(x) (((x) & 0x1) << 31) argument
42 #define PLL_RANGE_0MHZ 1
50 #define PLL_BYPASS_ENABLE 1
51 #define PLL_FSE_INTERNAL 1
[all …]
/Zephyr-latest/samples/sensor/magn_trig/
DREADME.rst9 Sample application that reads magnetometer (X, Y, Z) data from
36 fxos8700@1d (x, y, z): ( -0.107000, 0.118000, -1.026000)
37 fxos8700@1d (x, y, z): ( -0.132000, 0.083000, -0.981000)
38 fxos8700@1d (x, y, z): ( -0.143000, 0.102000, -0.931000)
39 fxos8700@1d (x, y, z): ( -0.153000, 0.126000, -0.843000)
40 fxos8700@1d (x, y, z): ( -0.145000, 0.152000, -0.802000)
41 fxos8700@1d (x, y, z): ( -0.143000, 0.125000, -0.740000)
42 fxos8700@1d (x, y, z): ( -0.133000, 0.130000, -0.736000)
43 fxos8700@1d (x, y, z): ( -0.133000, 0.124000, -0.776000)
44 fxos8700@1d (x, y, z): ( -0.120000, 0.123000, -0.776000)
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl362/
Dadxl362.h16 #define ADXL362_SLAVE_ID 1
60 #define ADXL362_STATUS_ERR_USER_REGS (1 << 7)
61 #define ADXL362_STATUS_AWAKE (1 << 6)
62 #define ADXL362_STATUS_INACT (1 << 5)
63 #define ADXL362_STATUS_ACT (1 << 4)
64 #define ADXL362_STATUS_FIFO_OVERRUN (1 << 3)
65 #define ADXL362_STATUS_FIFO_WATERMARK (1 << 2)
66 #define ADXL362_STATUS_FIFO_RDY (1 << 1)
67 #define ADXL362_STATUS_DATA_RDY (1 << 0)
70 #define ADXL362_ACT_INACT_CTL_LINKLOOP(x) (((x) & 0x3) << 4) argument
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl372/
Dadxl372.h38 #define ADXL372_STATUS_1 0x04u /* Status register 1 */
42 #define ADXL372_X_DATA_H 0x08u /* X-axis acceleration data [11:4] */
43 #define ADXL372_X_DATA_L 0x09u /* X-axis acceleration data [3:0] */
48 #define ADXL372_X_MAXPEAK_H 0x15u /* X-axis MaxPeak acceleration data */
49 #define ADXL372_X_MAXPEAK_L 0x16u /* X-axis MaxPeak acceleration data */
54 #define ADXL372_OFFSET_X 0x20u /* X axis offset */
57 #define ADXL372_X_THRESH_ACT_H 0x23u /* X axis Activity Threshold [15:8] */
58 #define ADXL372_X_THRESH_ACT_L 0x24u /* X axis Activity Threshold [7:0] */
64 #define ADXL372_X_THRESH_INACT_H 0x2Au /* X axis Inactivity Threshold */
65 #define ADXL372_X_THRESH_INACT_L 0x2Bu /* X axis Inactivity Threshold */
[all …]
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.h11 #define CDNS_HRS09_PHY_INIT_COMP BIT(1)
15 #define CDNS_HRS09_EXT_RD_MODE(x) ((x) << 2) argument
16 #define CDNS_HRS09_EXTENDED_WR(x) ((x) << 3) argument
17 #define CDNS_HRS09_RDCMD_EN(x) ((x) << 15) argument
18 #define CDNS_HRS09_RDDATA_EN(x) ((x) << 16) argument
30 /* SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up) */
32 #define DT_WIDTH BIT(1)
35 #define CDNS_SRS10_DTW 1
52 #define CDNS_SRS11_ICS BIT(1)
75 #define CDNS_SRS12_TC BIT(1)
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c17 #define STM32_SPI_DOMAIN_CLOCK_SUPPORT 1
53 if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { in ZTEST()
54 struct stm32_pclken spi1_domain_clk_cfg = pclken[1]; in ZTEST()
65 if (pclken[1].bus == STM32_SRC_PLL1_Q) { in ZTEST()
67 "Expected SPI src: PLL1 Q (0x%x). Actual: 0x%x", in ZTEST()
69 } else if (pclken[1].bus == STM32_SRC_PLL2_P) { in ZTEST()
71 "Expected SPI src: PLL2 P (0x%x). Actual: 0x%x", in ZTEST()
73 } else if (pclken[1].bus == STM32_SRC_PLL3_P) { in ZTEST()
75 "Expected SPI src: PLL3 P (0x%x). Actual: 0x%x", in ZTEST()
77 } else if (pclken[1].bus == STM32_SRC_CKPER) { in ZTEST()
[all …]
/Zephyr-latest/drivers/dma/
Ddma_dw_common.h18 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
19 #define SET_BIT(b, x) (((x) & 1) << (b)) argument
20 #define SET_BITS(b_hi, b_lo, x) \ argument
21 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
84 #define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
86 #define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
104 #define DW_CFGH_DST_PER_EXT(x) SET_BITS(31, 30, x) argument
105 #define DW_CFGH_SRC_PER_EXT(x) SET_BITS(29, 28, x) argument
106 #define DW_CFGH_DST_PER(x) SET_BITS(7, 4, x) argument
107 #define DW_CFGH_SRC_PER(x) SET_BITS(3, 0, x) argument
[all …]
/Zephyr-latest/doc/connectivity/networking/conn_mgr/figures/
Dintegration_diagram_detailed.drawio2 <diagram id="W1R5wPltpbE_ZV7s-k6x" name="Page-1">
3 … dy="1727" grid="0" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1"…
6 <mxCell id="1" parent="0" />
7 …138" value="" style="rounded=0;whiteSpace=wrap;html=1;dashed=1;fillColor=none;" parent="1" vertex=…
8 <mxGeometry x="516" y="-192" width="465" height="407" as="geometry" />
10 …"Db8zi3n4dXzB52SZQf6J-30" value="" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
11 <mxGeometry x="544" y="260" width="310" height="177" as="geometry" />
13 … style="text;html=1;strokeColor=none;fillColor=none;align=center;verticalAlign=middle;whiteSpace=w…
14 <mxGeometry x="646" y="-68" width="164" height="30" as="geometry" />
16 …lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;" parent="1" vertex…
[all …]
/Zephyr-latest/include/zephyr/math/
Dinterpolation.h28 * @param x_axis Ascending list of X co-ordinates for @a y_axis data points
29 * @param y_axis Y co-ordinates for each X data point
31 * @param x X co-ordinate to lookup
33 * @retval y_axis[0] if x < x_axis[0]
34 * @retval y_axis[len - 1] if x > x_axis[len - 1]
38 int32_t x) in linear_interpolate() argument
45 if (x <= x_axis[0]) { in linear_interpolate()
47 } else if (x >= x_axis[len - 1]) { in linear_interpolate()
48 return y_axis[len - 1]; in linear_interpolate()
51 /* Find the lower x axis bucket */ in linear_interpolate()
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl345/
Dadxl345.h36 #define ADXL345_REG_READ(x) ((x & 0xFF) | ADXL345_READ_CMD) argument
59 #define ADXL345_ENABLE_MEASURE_BIT (1 << 3)
60 #define ADXL345_FIFO_STREAM_MODE (1 << 7)
62 #define ADXL345_COMPLEMENT_MASK(x) GENMASK(15, (x)) argument
72 #define ADXL345_STATUS_DOUBLE_TAP(x) (((x) >> 5) & 0x1) argument
73 #define ADXL345_STATUS_SINGLE_TAP(x) (((x) >> 6) & 0x1) argument
74 #define ADXL345_STATUS_DATA_RDY(x) (((x) >> 7) & 0x1) argument
78 #define ADXL345_INT_MAP_OVERRUN_MODE(x) (((x) & 0x1) << 0) argument
79 #define ADXL345_INT_MAP_WATERMARK_MSK BIT(1)
80 #define ADXL345_INT_MAP_WATERMARK_MODE(x) (((x) & 0x1) << 1) argument
[all …]
/Zephyr-latest/dts/bindings/adc/
Dadc-controller.yaml15 const: 1
41 - ADC_GAIN_1_6: x 1/6
42 - ADC_GAIN_1_5: x 1/5
43 - ADC_GAIN_1_4: x 1/4
44 - ADC_GAIN_1_3: x 1/3
45 - ADC_GAIN_2_5: x 2/5
46 - ADC_GAIN_1_2: x 1/2
47 - ADC_GAIN_2_3: x 2/3
48 - ADC_GAIN_4_5: x 4/5
49 - ADC_GAIN_1: x 1
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dprci.h27 #define PLL_R(x) (((x) & 0x3f) << 0) argument
28 #define PLL_F(x) (((x) & 0x1ff) << 6) argument
29 #define PLL_Q(x) (((x) & 0x7) << 15) argument
30 #define PLL_RANGE(x) (((x) & 0x7) << 18) argument
31 #define PLL_BYPASS(x) (((x) & 0x1) << 24) argument
32 #define PLL_FSE(x) (((x) & 0x1) << 25) argument
33 #define PLL_LOCK(x) (((x) & 0x1) << 31) argument
37 #define PLL_BYPASS_ENABLE 1
38 #define PLL_FSE_INTERNAL 1
40 #define CORECLKSEL_CORECLKSEL(x) (((x) & 0x1) << 0) argument
[all …]
/Zephyr-latest/samples/boards/st/ccm/src/
Dmain.c22 #define CCM_DATA_ARRAY_VAL(i) (((i)+1)*0x11)
30 CCM_DATA_ARRAY_VAL(1),
43 printf("0x%02x ", ((const char *)array)[i]); in print_array()
55 check_failed = 1; in check_initial_var_values()
56 printf("\nccm_data_var_8 incorrect: 0x%02x should be 0x%02x", in check_initial_var_values()
61 check_failed = 1; in check_initial_var_values()
62 printf("\nccm_data_var_16 incorrect: 0x%04x should be 0x%04x", in check_initial_var_values()
67 check_failed = 1; in check_initial_var_values()
68 printf("\nccm_data_var_32 incorrect: 0x%08x should be 0x%08x", in check_initial_var_values()
74 check_failed = 1; in check_initial_var_values()
[all …]
/Zephyr-latest/subsys/bluetooth/mesh/shell/
Dcfg.c52 int32_t timeout_s = shell_strtol(argv[1], 0, &err); in cmd_timeout()
86 if (argc > 1) { in cmd_get_comp()
87 page = shell_strtoul(argv[1], 0, &err); in cmd_get_comp()
102 ((page != 1 && page != 129) || !IS_ENABLED(CONFIG_BT_MESH_COMP_PAGE_1)) && in cmd_get_comp()
117 shell_print(sh, "Got Composition Data for 0x%04x, page: %d:", in cmd_get_comp()
119 shell_print(sh, "\tCID 0x%04x", comp.cid); in cmd_get_comp()
120 shell_print(sh, "\tPID 0x%04x", comp.pid); in cmd_get_comp()
121 shell_print(sh, "\tVID 0x%04x", comp.vid); in cmd_get_comp()
122 shell_print(sh, "\tCRPL 0x%04x", comp.crpl); in cmd_get_comp()
123 shell_print(sh, "\tFeatures 0x%04x", comp.feat); in cmd_get_comp()
[all …]

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