11 #define CDNS_HRS09_PHY_INIT_COMP	BIT(1)
15 #define CDNS_HRS09_EXT_RD_MODE(x)	((x) << 2)  argument
16 #define CDNS_HRS09_EXTENDED_WR(x)	((x) << 3)  argument
17 #define CDNS_HRS09_RDCMD_EN(x)		((x) << 15)  argument
18 #define CDNS_HRS09_RDDATA_EN(x)		((x) << 16)  argument
30 /* SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up) */
32 #define DT_WIDTH BIT(1)
35 #define CDNS_SRS10_DTW		1
52 #define CDNS_SRS11_ICS		BIT(1)
75 #define CDNS_SRS12_TC			BIT(1)
80 #define BUFFER_BOUNDARY_8K   1U
96 #define CDNS_SRS15_SDR25		(1 << CDNS_SRS15_UMS)
100 /* V18SE is 0 for DS and HS, 1 for UHS-I */
103 /* HC4E is 0 means version 3.0 and 1 means v 4.0 */
122 #define CP_USE_EXT_LPBK_DQS(x)		(x << 22)  argument
123 #define CP_USE_LPBK_DQS(x)		(x << 21)  argument
124 #define CP_USE_PHONY_DQS(x)		(x << 20)  argument
125 #define CP_USE_PHONY_DQS_CMD(x)		(x << 19)  argument
128 #define CP_SYNC_METHOD(x)		((x) << 31)  argument
129 #define CP_SW_HALF_CYCLE_SHIFT(x)	((x) << 28)  argument
130 #define CP_RD_DEL_SEL(x)		((x) << 19)  argument
131 #define CP_UNDERRUN_SUPPRESS(x)		((x) << 18)  argument
132 #define CP_GATE_CFG_ALWAYS_ON(x)	((x) << 6)  argument
135 #define CP_DLL_BYPASS_MODE(x)		((x) << 23)  argument
136 #define CP_DLL_START_POINT(x)		((x) << 0)  argument
139 #define CP_READ_DQS_CMD_DELAY(x)	((x) << 24)  argument
140 #define CP_CLK_WRDQS_DELAY(x)		((x) << 16)  argument
141 #define CP_CLK_WR_DELAY(x)		((x) << 8)  argument
142 #define CP_READ_DQS_DELAY(x)		(x)  argument
145 #define CP_IO_MASK_ALWAYS_ON(x)		((x) << 31)  argument
146 #define CP_IO_MASK_END(x)		((x) << 27)  argument
147 #define CP_IO_MASK_START(x)		((x) << 24)  argument
148 #define CP_DATA_SELECT_OE_END(x)	(x)  argument
190 #define CDNS_SRS00_SAAR			1
201 #define CMD_SUSPEND_CMD			(1 << CDNS_SRS03_CMD_TYPE)
213 #define RES_TYPE_SEL_136		(1 << CDNS_SRS03_RES_TYPE_SEL)
220 #define AUTO_CMD12		(1 << CDNS_SRS03_ACE)
225 #define CDNS_SRS03_BLK_CNT_EN	BIT(1)
229 #define CDNS_HRS07_IDELAY_VAL(x)	(x)  argument
230 #define CDNS_HRS07_RW_COMPENSATE(x)	((x) << 16)  argument
239 #define SDHC_HRS10_HCSDCLKADJ(x)	((x) << 16)  argument
242 #define CDNS_HRS16_WRCMD0_DLY(x)        (x)  argument
243 #define CDNS_HRS16_WRCMD1_DLY(x)        ((x) << 4)  argument
244 #define CDNS_HRS16_WRDATA0_DLY(x)       ((x) << 8)  argument
245 #define CDNS_HRS16_WRDATA1_DLY(x)       ((x) << 12)  argument
246 #define CDNS_HRS16_WRCMD0_SDCLK_DLY(x)  ((x) << 16)  argument
247 #define CDNS_HRS16_WRCMD1_SDCLK_DLY(x)  ((x) << 20)  argument
248 #define CDNS_HRS16_WRDATA0_SDCLK_DLY(x) ((x) << 24)  argument
249 #define CDNS_HRS16_WRDATA1_SDCLK_DLY(x) ((x) << 28)  argument
257 #define MMC_BLOCK_MASK			(MMC_BLOCK_SIZE - 1)
277 #define MMC_RSP_136			BIT(1)	/* 136 bit response */
293 /* Value randomly chosen for eMMC RCA, it should be > 1 */
303 #define PART_CFG_PARTITION1_ACCESS	1
307 #define MMC_BUS_WIDTH_4			1
319 #define EXTCSD_CMD(x)			(((x) & 0xff) << 16)  argument
320 #define EXTCSD_VALUE(x)			(((x) & 0xff) << 8)  argument
321 #define EXTCSD_CMD_SET_NORMAL		1
327 #define STATUS_CURRENT_STATE(x)		(((x) & 0xf) << 9)  argument
330 #define MMC_GET_STATE(x)		(((x) >> 9) & 0xf)  argument
332 #define MMC_STATE_READY			1
343 #define MMC_FLAG_CMD23			1
353 #define ADMA_DESC_ATTR_END		BIT(1)