Lines Matching +full:1 +full:x
18 #define CNF_GET_INIT_COMP(x) (FIELD_GET(BIT(9), x)) argument
19 #define CNF_GET_INIT_FAIL(x) (FIELD_GET(BIT(10), x)) argument
20 #define CNF_GET_CTRL_BUSY(x) (FIELD_GET(BIT(8), x)) argument
21 #define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x)) argument
22 #define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x)) argument
23 #define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x)) argument
24 #define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x)) argument
25 #define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x)) argument
28 #define CNF_GET_NLUNS(x) (FIELD_GET(GENMASK(7, 0), x)) argument
29 #define CNF_GET_DEV_TYPE(x) (FIELD_GET(GENMASK(31, 30), x)) argument
48 #define CNF_HW_NF_16_SUPPORT(x) (FIELD_GET(BIT(29), x)) argument
49 #define CNF_HW_NVDDR_SS_SUPPORT(x) (FIELD_GET(BIT(27), x)) argument
50 #define CNF_HW_ASYNC_SUPPORT(x) (FIELD_GET(BIT(26), x)) argument
51 #define CNF_HW_DMA_DATA_WIDTH_SUPPORT(x) (FIELD_GET(BIT(21), x)) argument
52 #define CNF_HW_DMA_ADDR_WIDTH_SUPPORT(x) (FIELD_GET(BIT(20), x)) argument
53 #define CNF_HW_DI_PR_SUPPORT(x) (FIELD_GET(BIT(14), x)) argument
54 #define CNF_HW_ECC_SUPPORT(x) (FIELD_GET(BIT(17), x)) argument
55 #define CNF_HW_RMP_SUPPORT(x) (FIELD_GET(BIT(12), x)) argument
56 #define CNF_HW_DI_CRC_SUPPORT(x) (FIELD_GET(BIT(8), x)) argument
57 #define CNF_HW_WR_PT_SUPPORT(x) (FIELD_GET(BIT(9), x)) argument
83 #define CNF_DI_CRC_EN (1)
97 #define CNF_OPR_WORK_MODE_NVDDR (1)
98 #define CNF_OPR_WORK_MODE_SDR_MASK (GENMASK(1, 0))
142 #define INTERRUPT_ENABLE (1)
151 #define DMA_MS_SEL (1)
154 #define CDMA_CF_DMA_MASTER_SET(x) FIELD_PREP(BIT(CDMA_CF_DMA_MASTER), x) argument
156 #define F_CFLAGS_VOL_ID_SET(x) FIELD_PREP(GENMASK(7, 4), x) argument
161 #define CDNS_WRITE (1)
164 #define CFLAGS_MPTRPC_SET FIELD_PREP(BIT(CFLAGS_MPTRPC), 1)
165 #define CFLAGS_FPTRPC (1)
166 #define CFLAGS_FPTRPC_SET FIELD_PREP(BIT(CFLAGS_FPTRPC), 1)
168 #define CFLAGS_CONT_SET FIELD_PREP(BIT(CFLAGS_CONT), 1)
170 #define ENABLE (1)
185 #define CT_PIO_MODE (1)
188 #define OPERATING_MODE_PIO (1)
193 #define CMD_0_THREAD_POS_SET(x) (FIELD_PREP(GENMASK(26, 24), x)) argument
195 #define CMD_0_C_MODE_SET(x) (FIELD_PREP(GENMASK(31, 30), x)) argument
196 #define CMD_0_VOL_ID_SET(x) (FIELD_PREP(GENMASK(19, 16), x)) argument
206 #define F_BURST_SEL_SET(x) (FIELD_PREP(GENMASK(7, 0), x)) argument
213 #define NF_FIFO_TRIGG_LVL_SET(x) (FIELD_PREP(GENMASK(15, 0), x)) argument
214 #define NF_DMA_PACKAGE_SIZE_SET(x) (FIELD_PREP(GENMASK(31, 16), x)) argument
223 #define HPNFC_STAT_OK (1)
224 #define NF_16_ENABLE (1)
228 #define NF_CMD4_BANK_SET(x) (FIELD_PREP(GENMASK(31, 24), x)) argument
230 #define PIO_CMD0_CT_SET(x) (FIELD_PREP(GENMASK(15, 0), x)) argument
232 #define PIO_CF_INT_SET (FIELD_PREP(BIT(PIO_CF_INT), 1))
234 #define PIO_CF_DMA_MASTER_SET(x) (FIELD_PREP(BIT(PIO_CF_DMA_MASTER), x)) argument
262 #define GCMCD_ADDR_SEQ (1)
265 #define GEN_SECTOR_COUNT (1ULL)
269 #define GEN_LAST_SECTOR_SIZE_SET(x) (FIELD_PREP(GENMASK64(55, 40), x)) argument
280 #define PAGE_MAX_BYTES(x) (FIELD_PREP(GENMASK64(13, 11), x)) argument
282 #define GEN_CF_INT_SET(x) (FIELD_PREP(BIT(GEN_CF_INT), x)) argument
283 #define GEN_CF_INT_ENABLE (1)
285 #define GEN_DIR_SET(x) (FIELD_PREP(BIT64(11), x)) argument
286 #define GEN_SECTOR_SET(x) (FIELD_PREP(GENMASK64(31, 16), x)) argument
288 #define GEN_ADDR_WRITE_DATA(x) (FIELD_PREP(GENMASK64(63, 32), x)) argument
289 #define NUM_ONE (1)
293 #define ROW_VAL_SET(x, y, z) (FIELD_PREP(GENMASK(x, y), z)) argument
294 #define SET_FEAT_ADDR(x) (FIELD_PREP(GENMASK(7, 0), x)) argument
295 #define THREAD_VAL(x) (FIELD_PREP(GENMASK(2, 0), x)) argument
296 #define INCR_CMD_TYPE(x) (x++) argument
297 #define DECR_CNT_ONE(x) (--x) argument
298 #define GET_INIT_SET_CHECK(x, y) (FIELD_GET(BIT(y), x)) argument