11 #define MAX14906_ENABLE  1
36 #define MAX149x6_ADDR_MASK      GENMASK(4, 1)
40 #define MAX149x6_DOI_LEVEL_MASK(x) BIT(x)  argument
43 #define MAX14906_HIGHO_MASK(x) BIT(x)  argument
45 #define MAX14906_DO_MASK(x)     (GENMASK(1, 0) << (2 * (x)))  argument
46 #define MAX14906_CH_DIR_MASK(x) BIT((x) + 4)  argument
47 #define MAX14906_CH(x)          (x)  argument
49 #define MAX14906_CL_MASK(x)     (GENMASK(1, 0) << (2 * (x)))  argument
52 #define MAX14906_SLED_MASK BIT(1)
55 #define MAX14906_CHAN_MASK_LSB(x) BIT(x)  argument
56 #define MAX14906_CHAN_MASK_MSB(x) BIT((x) + 4)  argument
60 	MAX14906_ADDR_1, /* A0=1, A1=0 */
61 	MAX14906_ADDR_2, /* A0=0, A1=1 */
62 	MAX14906_ADDR_3, /* A0=1, A1=1 */
101 		uint8_t OVER_LD_FLT: 1; /* BIT0 */
102 		uint8_t CURR_LIM: 1;
103 		uint8_t OW_OFF_FLT: 1;
104 		uint8_t OW_ON_FLT: 1;
105 		uint8_t SHT_VDD_FLT: 1;
106 		uint8_t DE_MAG_FLT: 1;
107 		uint8_t SUPPLY_ERR: 1;
108 		uint8_t COM_ERR: 1; /* BIT7 */
115 		uint8_t FLED_SET: 1; /* BIT0 */
116 		uint8_t SLED_SET: 1;
118 		uint8_t FFILTER_EN: 1;
119 		uint8_t FILTER_LONG: 1;
120 		uint8_t FLATCH_EN: 1;
121 		uint8_t LED_CURR_LIM: 1; /* BIT7 */
128 		uint8_t VDD_ON_THR: 1; /* BIT0 */
129 		uint8_t SYNCH_WD_EN: 1;
139 		uint8_t OVER_LD_M: 1; /* BIT0 */
140 		uint8_t CURR_LIM_M: 1;
141 		uint8_t OW_OFF_M: 1;
142 		uint8_t OW_ON_M: 1;
143 		uint8_t SHT_VDD_M: 1;
144 		uint8_t VDD_OK_M: 1;
145 		uint8_t SUPPLY_ERR_M: 1;
146 		uint8_t COM_ERR_M: 1; /* BIT7 */
153 		uint8_t VINT_UV: 1; /* BIT0 */
154 		uint8_t VA_UVLO: 1;
155 		uint8_t VDD_BAD: 1;
156 		uint8_t VDD_WARN: 1;
157 		uint8_t VDD_UVLO: 1;
158 		uint8_t THRMSHUTD: 1;
159 		uint8_t SYNC_ERR: 1;
160 		uint8_t WDOG_ERR: 1; /* BIT7 */