1 /* 2 * Copyright (c) 2024 Analog Devices Inc. 3 * Copyright (c) 2024 Baylibre SAS 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_GPIO_GPIO_MAX14916_H_ 9 #define ZEPHYR_DRIVERS_GPIO_GPIO_MAX14916_H_ 10 11 #define MAX14906_ENABLE 1 12 #define MAX14906_DISABLE 0 13 14 #define MAX149x6_MAX_PKT_SIZE 3 15 16 #define MAX14916_CHANNELS 8 17 18 #define MAX14916_SETOUT_REG 0x0 19 #define MAX14916_SET_FLED_REG 0x1 20 #define MAX14916_SET_SLED_REG 0x2 21 #define MAX14916_INT_REG 0x3 22 #define MAX14916_OVR_LD_REG 0x4 23 #define MAX14916_CURR_LIM_REG 0x5 24 #define MAX14916_OW_OFF_FLT_REG 0x6 25 #define MAX14916_OW_ON_FLT_REG 0x7 26 #define MAX14916_SHT_VDD_FLT_REG 0x8 27 #define MAX14916_GLOB_ERR_REG 0x9 28 #define MAX14916_OW_OFF_EN_REG 0xA 29 #define MAX14916_OW_ON_EN_REG 0xB 30 #define MAX14916_SHT_VDD_EN_REG 0xC 31 #define MAX14916_CONFIG1_REG 0xD 32 #define MAX14916_CONFIG2_REG 0xE 33 #define MAX14916_CONFIG_MASK 0xF 34 35 #define MAX149x6_CHIP_ADDR_MASK GENMASK(7, 6) 36 #define MAX149x6_ADDR_MASK GENMASK(4, 1) 37 #define MAX149x6_RW_MASK BIT(0) 38 39 /* DoiLevel register */ 40 #define MAX149x6_DOI_LEVEL_MASK(x) BIT(x) 41 42 /* SetOUT register */ 43 #define MAX14906_HIGHO_MASK(x) BIT(x) 44 45 #define MAX14906_DO_MASK(x) (GENMASK(1, 0) << (2 * (x))) 46 #define MAX14906_CH_DIR_MASK(x) BIT((x) + 4) 47 #define MAX14906_CH(x) (x) 48 #define MAX14906_IEC_TYPE_MASK BIT(7) 49 #define MAX14906_CL_MASK(x) (GENMASK(1, 0) << (2 * (x))) 50 51 /* Config1 register */ 52 #define MAX14906_SLED_MASK BIT(1) 53 #define MAX14906_FLED_MASK BIT(0) 54 55 #define MAX14906_CHAN_MASK_LSB(x) BIT(x) 56 #define MAX14906_CHAN_MASK_MSB(x) BIT((x) + 4) 57 58 enum max149x6_spi_addr { 59 MAX14906_ADDR_0, /* A0=0, A1=0 */ 60 MAX14906_ADDR_1, /* A0=1, A1=0 */ 61 MAX14906_ADDR_2, /* A0=0, A1=1 */ 62 MAX14906_ADDR_3, /* A0=1, A1=1 */ 63 }; 64 65 enum max14916_fled_time { 66 MAX14916_FLED_TIME_DISABLED, 67 MAX14916_FLED_TIME_1S, 68 MAX14916_FLED_TIME_2S, 69 MAX14916_FLED_TIME_3S 70 }; 71 72 enum max14916_sled_state { 73 MAX14916_SLED_OFF, 74 MAX14916_SLED_ON 75 }; 76 77 enum max14916_wd { 78 MAX14916_WD_DISABLED, 79 MAX14916_WD_200MS, 80 MAX14916_WD_600MS, 81 MAX14916_WD_1200MS 82 }; 83 84 enum max14916_ow_off_cs { 85 MAX14916_OW_OFF_CS_20UA, 86 MAX14916_OW_OFF_CS_100UA, 87 MAX14916_OW_OFF_CS_300UA, 88 MAX14916_OW_OFF_CS_600UA 89 }; 90 91 enum max14916_sht_vdd_thr { 92 MAX14916_SHT_VDD_THR_9V, 93 MAX14916_SHT_VDD_THR_10V, 94 MAX14916_SHT_VDD_THR_12V, 95 MAX14916_SHT_VDD_THR_14V 96 }; 97 98 union max14916_interrupt { 99 uint8_t reg_raw; 100 struct { 101 uint8_t OVER_LD_FLT: 1; /* BIT0 */ 102 uint8_t CURR_LIM: 1; 103 uint8_t OW_OFF_FLT: 1; 104 uint8_t OW_ON_FLT: 1; 105 uint8_t SHT_VDD_FLT: 1; 106 uint8_t DE_MAG_FLT: 1; 107 uint8_t SUPPLY_ERR: 1; 108 uint8_t COM_ERR: 1; /* BIT7 */ 109 } reg_bits; 110 }; 111 112 union max14916_config1 { 113 uint8_t reg_raw; 114 struct { 115 uint8_t FLED_SET: 1; /* BIT0 */ 116 uint8_t SLED_SET: 1; 117 uint8_t FLED_STRETCH: 2; 118 uint8_t FFILTER_EN: 1; 119 uint8_t FILTER_LONG: 1; 120 uint8_t FLATCH_EN: 1; 121 uint8_t LED_CURR_LIM: 1; /* BIT7 */ 122 } reg_bits; 123 }; 124 125 union max14916_config2 { 126 uint8_t reg_raw; 127 struct { 128 uint8_t VDD_ON_THR: 1; /* BIT0 */ 129 uint8_t SYNCH_WD_EN: 1; 130 uint8_t SHT_VDD_THR: 2; 131 uint8_t OW_OFF_CS: 2; 132 uint8_t WD_TO: 2; /* BIT7 */ 133 } reg_bits; 134 }; 135 136 union max14916_mask { 137 uint8_t reg_raw; 138 struct { 139 uint8_t OVER_LD_M: 1; /* BIT0 */ 140 uint8_t CURR_LIM_M: 1; 141 uint8_t OW_OFF_M: 1; 142 uint8_t OW_ON_M: 1; 143 uint8_t SHT_VDD_M: 1; 144 uint8_t VDD_OK_M: 1; 145 uint8_t SUPPLY_ERR_M: 1; 146 uint8_t COM_ERR_M: 1; /* BIT7 */ 147 } reg_bits; 148 }; 149 150 union max14916_global_err { 151 uint8_t reg_raw; 152 struct { 153 uint8_t VINT_UV: 1; /* BIT0 */ 154 uint8_t VA_UVLO: 1; 155 uint8_t VDD_BAD: 1; 156 uint8_t VDD_WARN: 1; 157 uint8_t VDD_UVLO: 1; 158 uint8_t THRMSHUTD: 1; 159 uint8_t SYNC_ERR: 1; 160 uint8_t WDOG_ERR: 1; /* BIT7 */ 161 } reg_bits; 162 }; 163 164 struct max149x6_config { 165 struct spi_dt_spec spi; 166 struct gpio_dt_spec fault_gpio; 167 struct gpio_dt_spec ready_gpio; 168 struct gpio_dt_spec sync_gpio; 169 struct gpio_dt_spec en_gpio; 170 bool crc_en; 171 union max14916_config1 config1; 172 union max14916_config2 config2; 173 enum max149x6_spi_addr spi_addr; 174 uint8_t pkt_size; 175 }; 176 177 #define max14916_config max149x6_config 178 179 struct max14916_data { 180 struct gpio_driver_data common; 181 struct { 182 uint8_t ovr_ld; 183 uint8_t curr_lim; 184 uint8_t ow_off; 185 uint8_t ow_on; 186 uint8_t sht_vdd; 187 } chan; 188 struct { 189 uint8_t ow_off_en; 190 uint8_t ow_on_en; 191 uint8_t sht_vdd_en; 192 } chan_en; 193 struct { 194 union max14916_interrupt interrupt; 195 union max14916_global_err glob_err; 196 union max14916_mask mask; 197 } glob; 198 }; 199 200 #endif 201
