36 #define ADXL345_REG_READ(x)	((x & 0xFF) | ADXL345_READ_CMD)  argument
59 #define ADXL345_ENABLE_MEASURE_BIT (1 << 3)
60 #define ADXL345_FIFO_STREAM_MODE   (1 << 7)
62 #define ADXL345_COMPLEMENT_MASK(x) GENMASK(15, (x))  argument
72 #define ADXL345_STATUS_DOUBLE_TAP(x) (((x) >> 5) & 0x1)  argument
73 #define ADXL345_STATUS_SINGLE_TAP(x) (((x) >> 6) & 0x1)  argument
74 #define ADXL345_STATUS_DATA_RDY(x)   (((x) >> 7) & 0x1)  argument
78 #define ADXL345_INT_MAP_OVERRUN_MODE(x)    (((x) & 0x1) << 0)  argument
79 #define ADXL345_INT_MAP_WATERMARK_MSK      BIT(1)
80 #define ADXL345_INT_MAP_WATERMARK_MODE(x)  (((x) & 0x1) << 1)  argument
82 #define ADXL345_INT_MAP_FREE_FALL_MODE(x)  (((x) & 0x1) << 2)  argument
84 #define ADXL345_INT_MAP_INACT_MODE(x)      (((x) & 0x1) << 3)  argument
86 #define ADXL345_INT_MAP_ACT_MODE(x)        (((x) & 0x1) << 4)  argument
88 #define ADXL345_INT_MAP_DOUBLE_TAP_MODE(x) (((x) & 0x1) << 5)  argument
90 #define ADXL345_INT_MAP_SINGLE_TAP_MODE(x) (((x) & 0x1) << 6)  argument
92 #define ADXL345_INT_MAP_DATA_RDY_MODE(x)   (((x) & 0x1) << 7)  argument
96 #define ADXL345_POWER_CTL_WAKEUP_4HZ_MODE(x) (((x) & 0x1) << 0)  argument
97 #define ADXL345_POWER_CTL_WAKEUP_2HZ         BIT(1)
98 #define ADXL345_POWER_CTL_WAKEUP_2HZ_MODE(x) (((x) & 0x1) << 1)  argument
100 #define ADXL345_POWER_CTL_SLEEP_MODE(x)      (((x) & 0x1) << 2)  argument
102 #define ADXL345_POWER_CTL_MEASURE_MODE(x)    (((x) & 0x1) << 3)  argument
103 #define ADXL345_POWER_CTL_STANDBY_MODE(x)    (((x) & 0x0) << 3)  argument
107 #define ADXL345_FIFO_CTL_MODE_MODE(x)    (((x) & 0x3) << 6)  argument
109 #define ADXL345_FIFO_CTL_TRIGGER_MODE(x) (((x) & 0x1) << 5)  argument
111 #define ADXL345_FIFO_CTL_SAMPLES_MODE(x) ((x) & 0x1F)  argument
114 #define ADXL345_ODR_MODE(x) ((x) & 0xF)  argument
117 #define ADXL345_BUS_SPI 1
181 	uint8_t fifo_ent[1];
191 	uint8_t is_fifo: 1;
192 	uint8_t is_full_res: 1;
203 	uint8_t is_fifo: 1;
207 	int16_t x;  member