16 #define ADXL362_SLAVE_ID    1
60 #define ADXL362_STATUS_ERR_USER_REGS        (1 << 7)
61 #define ADXL362_STATUS_AWAKE                (1 << 6)
62 #define ADXL362_STATUS_INACT                (1 << 5)
63 #define ADXL362_STATUS_ACT                  (1 << 4)
64 #define ADXL362_STATUS_FIFO_OVERRUN         (1 << 3)
65 #define ADXL362_STATUS_FIFO_WATERMARK       (1 << 2)
66 #define ADXL362_STATUS_FIFO_RDY             (1 << 1)
67 #define ADXL362_STATUS_DATA_RDY             (1 << 0)
70 #define ADXL362_ACT_INACT_CTL_LINKLOOP(x)   (((x) & 0x3) << 4)  argument
71 #define ADXL362_ACT_INACT_CTL_INACT_REF     (1 << 3)
72 #define ADXL362_ACT_INACT_CTL_INACT_EN      (1 << 2)
73 #define ADXL362_ACT_INACT_CTL_ACT_REF       (1 << 1)
74 #define ADXL362_ACT_INACT_CTL_ACT_EN        (1 << 0)
76 /* ADXL362_ACT_INACT_CTL_LINKLOOP(x) options */
78 #define ADXL362_MODE_LINK           1
82 #define ADXL362_FIFO_CTL_AH                 (1 << 3)
83 #define ADXL362_FIFO_CTL_FIFO_TEMP          (1 << 2)
84 #define ADXL362_FIFO_CTL_FIFO_MODE(x)       (((x) & 0x3) << 0)  argument
86 /* ADXL362_FIFO_CTL_FIFO_MODE(x) options */
88 #define ADXL362_FIFO_OLDEST_SAVED         1
93 #define ADXL362_INTMAP1_INT_LOW             (1 << 7)
94 #define ADXL362_INTMAP1_AWAKE               (1 << 6)
95 #define ADXL362_INTMAP1_INACT               (1 << 5)
96 #define ADXL362_INTMAP1_ACT                 (1 << 4)
97 #define ADXL362_INTMAP1_FIFO_OVERRUN        (1 << 3)
98 #define ADXL362_INTMAP1_FIFO_WATERMARK      (1 << 2)
99 #define ADXL362_INTMAP1_FIFO_READY          (1 << 1)
100 #define ADXL362_INTMAP1_DATA_READY          (1 << 0)
103 #define ADXL362_INTMAP2_INT_LOW             (1 << 7)
104 #define ADXL362_INTMAP2_AWAKE               (1 << 6)
105 #define ADXL362_INTMAP2_INACT               (1 << 5)
106 #define ADXL362_INTMAP2_ACT                 (1 << 4)
107 #define ADXL362_INTMAP2_FIFO_OVERRUN        (1 << 3)
108 #define ADXL362_INTMAP2_FIFO_WATERMARK      (1 << 2)
109 #define ADXL362_INTMAP2_FIFO_READY          (1 << 1)
110 #define ADXL362_INTMAP2_DATA_READY          (1 << 0)
113 #define ADXL362_FILTER_CTL_RANGE(x)         (((x) & 0x3) << 6)  argument
114 #define ADXL362_FILTER_CTL_RES              (1 << 5)
115 #define ADXL362_FILTER_CTL_HALF_BW          (1 << 4)
116 #define ADXL362_FILTER_CTL_EXT_SAMPLE       (1 << 3)
117 #define ADXL362_FILTER_CTL_ODR(x)           (((x) & 0x7) << 0)  argument
119 /* ADXL362_FILTER_CTL_RANGE(x) options */
121 #define ADXL362_RANGE_4G                1       /* +/-4 g */
124 /* ADXL362_FILTER_CTL_ODR(x) options */
126 #define ADXL362_ODR_25_HZ               1       /* 25 Hz */
133 #define ADXL362_POWER_CTL_RES               (1 << 7)
134 #define ADXL362_POWER_CTL_EXT_CLK           (1 << 6)
135 #define ADXL362_POWER_CTL_LOW_NOISE(x)      (((x) & 0x3) << 4)  argument
136 #define ADXL362_POWER_CTL_WAKEUP            (1 << 3)
137 #define ADXL362_POWER_CTL_AUTOSLEEP         (1 << 2)
138 #define ADXL362_POWER_CTL_MEASURE(x)        (((x) & 0x3) << 0)  argument
140 /* ADXL362_POWER_CTL_LOW_NOISE(x) options */
142 #define ADXL362_NOISE_MODE_LOW              1
145 /* ADXL362_POWER_CTL_MEASURE(x) options */
150 #define ADXL362_SELF_TEST_ST            (1 << 0)
161 #define ADXL362_STATUS_CHECK_DATA_READY(x)	(((x) >> 0) & 0x1)  argument
162 #define ADXL362_STATUS_CHECK_INACT(x)		(((x) >> 5) & 0x1)  argument
163 #define ADXL362_STATUS_CHECK_ACTIVITY(x)	(((x) >> 4) & 0x1)  argument
164 #define ADXL362_STATUS_CHECK_FIFO_OVR(x)	(((x) >> 3) & 0x1)  argument
165 #define ADXL362_STATUS_CHECK_FIFO_WTR(x)	(((x) >> 2) & 0x1)  argument
178 #define ADXL362_FIFO_HDR_CHECK_ACCEL_X(x)	((((x) & 0xC000) >> 14) == 0x00)  argument
179 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Y(x)	((((x) & 0xC000) >> 14) == 0x01)  argument
180 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Z(x)	((((x) & 0xC000) >> 14) == 0x02)  argument
181 #define ADXL362_FIFO_HDR_CHECK_TEMP(x)	((((x) & 0xC000) >> 14) == 0x03)  argument
238 	uint8_t fifo_full_irq: 1;
239 	uint8_t fifo_wmark_irq: 1;
246 	uint8_t is_fifo: 1;
257 	uint8_t is_fifo: 1;
258 	uint8_t has_tmp: 1;