1 /* 2 * Copyright (c) 2018 Analog Devices Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ 9 10 #include <zephyr/drivers/sensor.h> 11 #include <zephyr/types.h> 12 #include <zephyr/device.h> 13 #include <zephyr/drivers/gpio.h> 14 #include <zephyr/kernel.h> 15 #include <zephyr/sys/util.h> 16 17 #ifdef CONFIG_ADXL372_STREAM 18 #include <zephyr/rtio/rtio.h> 19 #endif /* CONFIG_ADXL372_STREAM */ 20 21 #define DT_DRV_COMPAT adi_adxl372 22 23 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 24 #include <zephyr/drivers/spi.h> 25 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 26 27 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 28 #include <zephyr/drivers/i2c.h> 29 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 30 31 /* 32 * ADXL372 registers definition 33 */ 34 #define ADXL372_DEVID 0x00u /* Analog Devices accelerometer ID */ 35 #define ADXL372_DEVID_MST 0x01u /* Analog Devices MEMS device ID */ 36 #define ADXL372_PARTID 0x02u /* Device ID */ 37 #define ADXL372_REVID 0x03u /* product revision ID*/ 38 #define ADXL372_STATUS_1 0x04u /* Status register 1 */ 39 #define ADXL372_STATUS_2 0x05u /* Status register 2 */ 40 #define ADXL372_FIFO_ENTRIES_2 0x06u /* Valid data samples in the FIFO */ 41 #define ADXL372_FIFO_ENTRIES_1 0x07u /* Valid data samples in the FIFO */ 42 #define ADXL372_X_DATA_H 0x08u /* X-axis acceleration data [11:4] */ 43 #define ADXL372_X_DATA_L 0x09u /* X-axis acceleration data [3:0] */ 44 #define ADXL372_Y_DATA_H 0x0Au /* Y-axis acceleration data [11:4] */ 45 #define ADXL372_Y_DATA_L 0x0Bu /* Y-axis acceleration data [3:0] */ 46 #define ADXL372_Z_DATA_H 0x0Cu /* Z-axis acceleration data [11:4] */ 47 #define ADXL372_Z_DATA_L 0x0Du /* Z-axis acceleration data [3:0] */ 48 #define ADXL372_X_MAXPEAK_H 0x15u /* X-axis MaxPeak acceleration data */ 49 #define ADXL372_X_MAXPEAK_L 0x16u /* X-axis MaxPeak acceleration data */ 50 #define ADXL372_Y_MAXPEAK_H 0x17u /* Y-axis MaxPeak acceleration data */ 51 #define ADXL372_Y_MAXPEAK_L 0x18u /* Y-axis MaxPeak acceleration data */ 52 #define ADXL372_Z_MAXPEAK_H 0x19u /* Z-axis MaxPeak acceleration data */ 53 #define ADXL372_Z_MAXPEAK_L 0x1Au /* Z-axis MaxPeak acceleration data */ 54 #define ADXL372_OFFSET_X 0x20u /* X axis offset */ 55 #define ADXL372_OFFSET_Y 0x21u /* Y axis offset */ 56 #define ADXL372_OFFSET_Z 0x22u /* Z axis offset */ 57 #define ADXL372_X_THRESH_ACT_H 0x23u /* X axis Activity Threshold [15:8] */ 58 #define ADXL372_X_THRESH_ACT_L 0x24u /* X axis Activity Threshold [7:0] */ 59 #define ADXL372_Y_THRESH_ACT_H 0x25u /* Y axis Activity Threshold [15:8] */ 60 #define ADXL372_Y_THRESH_ACT_L 0x26u /* Y axis Activity Threshold [7:0] */ 61 #define ADXL372_Z_THRESH_ACT_H 0x27u /* Z axis Activity Threshold [15:8] */ 62 #define ADXL372_Z_THRESH_ACT_L 0x28u /* Z axis Activity Threshold [7:0] */ 63 #define ADXL372_TIME_ACT 0x29u /* Activity Time */ 64 #define ADXL372_X_THRESH_INACT_H 0x2Au /* X axis Inactivity Threshold */ 65 #define ADXL372_X_THRESH_INACT_L 0x2Bu /* X axis Inactivity Threshold */ 66 #define ADXL372_Y_THRESH_INACT_H 0x2Cu /* Y axis Inactivity Threshold */ 67 #define ADXL372_Y_THRESH_INACT_L 0x2Du /* Y axis Inactivity Threshold */ 68 #define ADXL372_Z_THRESH_INACT_H 0x2Eu /* Z axis Inactivity Threshold */ 69 #define ADXL372_Z_THRESH_INACT_L 0x2Fu /* Z axis Inactivity Threshold */ 70 #define ADXL372_TIME_INACT_H 0x30u /* Inactivity Time [15:8] */ 71 #define ADXL372_TIME_INACT_L 0x31u /* Inactivity Time [7:0] */ 72 #define ADXL372_X_THRESH_ACT2_H 0x32u /* X axis Activity2 Threshold [15:8] */ 73 #define ADXL372_X_THRESH_ACT2_L 0x33u /* X axis Activity2 Threshold [7:0] */ 74 #define ADXL372_Y_THRESH_ACT2_H 0x34u /* Y axis Activity2 Threshold [15:8] */ 75 #define ADXL372_Y_THRESH_ACT2_L 0x35u /* Y axis Activity2 Threshold [7:0] */ 76 #define ADXL372_Z_THRESH_ACT2_H 0x36u /* Z axis Activity2 Threshold [15:8] */ 77 #define ADXL372_Z_THRESH_ACT2_L 0x37u /* Z axis Activity2 Threshold [7:0] */ 78 #define ADXL372_HPF 0x38u /* High Pass Filter */ 79 #define ADXL372_FIFO_SAMPLES 0x39u /* FIFO Samples */ 80 #define ADXL372_FIFO_CTL 0x3Au /* FIFO Control */ 81 #define ADXL372_INT1_MAP 0x3Bu /* Interrupt 1 mapping control */ 82 #define ADXL372_INT2_MAP 0x3Cu /* Interrupt 2 mapping control */ 83 #define ADXL372_TIMING 0x3Du /* Timing */ 84 #define ADXL372_MEASURE 0x3Eu /* Measure */ 85 #define ADXL372_POWER_CTL 0x3Fu /* Power control */ 86 #define ADXL372_SELF_TEST 0x40u /* Self Test */ 87 #define ADXL372_RESET 0x41u /* Reset */ 88 #define ADXL372_FIFO_DATA 0x42u /* FIFO Data */ 89 90 #define ADXL372_DEVID_VAL 0xADu /* Analog Devices accelerometer ID */ 91 #define ADXL372_MST_DEVID_VAL 0x1Du /* Analog Devices MEMS device ID */ 92 #define ADXL372_PARTID_VAL 0xFAu /* Device ID */ 93 #define ADXL372_REVID_VAL 0x02u /* product revision ID*/ 94 #define ADXL372_RESET_CODE 0x52u /* Writing code 0x52 resets the device */ 95 96 #define ADXL372_READ 0x01u 97 #define ADXL372_REG_READ(x) (((x & 0xFF) << 1) | ADXL372_READ) 98 #define ADXL372_REG_WRITE(x) ((x & 0xFF) << 1) 99 #define ADXL372_TO_I2C_REG(x) ((x) >> 1) 100 101 /* ADXL372_POWER_CTL */ 102 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MSK BIT(5) 103 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MODE(x) (((x) & 0x1) << 5) 104 #define ADXL372_POWER_CTL_FIL_SETTLE_MSK BIT(4) 105 #define ADXL372_POWER_CTL_FIL_SETTLE_MODE(x) (((x) & 0x1) << 4) 106 #define ADXL372_POWER_CTL_LPF_DIS_MSK BIT(3) 107 #define ADXL372_POWER_CTL_LPF_DIS_MODE(x) (((x) & 0x1) << 3) 108 #define ADXL372_POWER_CTL_HPF_DIS_MSK BIT(2) 109 #define ADXL372_POWER_CTL_HPF_DIS_MODE(x) (((x) & 0x1) << 2) 110 #define ADXL372_POWER_CTL_MODE_MSK GENMASK(1, 0) 111 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0) 112 113 /* ADXL372_MEASURE */ 114 #define ADXL372_MEASURE_AUTOSLEEP_MSK BIT(6) 115 #define ADXL372_MEASURE_AUTOSLEEP_MODE(x) (((x) & 0x1) << 6) 116 #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK(5, 4) 117 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4) 118 #define ADXL372_MEASURE_LOW_NOISE_MSK BIT(3) 119 #define ADXL372_MEASURE_LOW_NOISE_MODE(x) (((x) & 0x1) << 3) 120 #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK(2, 0) 121 #define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0) 122 123 /* ADXL372_TIMING */ 124 #define ADXL372_TIMING_ODR_MSK GENMASK(7, 5) 125 #define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5) 126 #define ADXL372_TIMING_WAKE_UP_RATE_MSK GENMASK(4, 2) 127 #define ADXL372_TIMING_WAKE_UP_RATE_MODE(x) (((x) & 0x7) << 2) 128 #define ADXL372_TIMING_EXT_CLK_MSK BIT(1) 129 #define ADXL372_TIMING_EXT_CLK_MODE(x) (((x) & 0x1) << 1) 130 #define ADXL372_TIMING_EXT_SYNC_MSK BIT(0) 131 #define ADXL372_TIMING_EXT_SYNC_MODE(x) (((x) & 0x1) << 0) 132 133 /* ADXL372_FIFO_CTL */ 134 #define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3) 135 #define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3) 136 #define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1) 137 #define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1) 138 #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(0) 139 #define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0) 140 141 /* ADXL372_STATUS_1 */ 142 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1) 143 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1) 144 #define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1) 145 #define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1) 146 #define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1) 147 #define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1) 148 #define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1) 149 150 /* ADXL372_STATUS_2 */ 151 #define ADXL372_STATUS_2_INACT(x) (((x) >> 4) & 0x1) 152 #define ADXL372_STATUS_2_ACTIVITY(x) (((x) >> 5) & 0x1) 153 #define ADXL372_STATUS_2_ACTIVITY2(x) (((x) >> 6) & 0x1) 154 155 /* ADXL372_INT1_MAP */ 156 #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0) 157 #define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0) 158 #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1) 159 #define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1) 160 #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2) 161 #define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2) 162 #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3) 163 #define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3) 164 #define ADXL372_INT1_MAP_INACT_MSK BIT(4) 165 #define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4) 166 #define ADXL372_INT1_MAP_ACT_MSK BIT(5) 167 #define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5) 168 #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6) 169 #define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6) 170 #define ADXL372_INT1_MAP_LOW_MSK BIT(7) 171 #define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7) 172 173 /* ADXL372_INT2_MAP */ 174 #define ADXL372_INT2_MAP_DATA_RDY_MSK BIT(0) 175 #define ADXL372_INT2_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0) 176 #define ADXL372_INT2_MAP_FIFO_RDY_MSK BIT(1) 177 #define ADXL372_INT2_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1) 178 #define ADXL372_INT2_MAP_FIFO_FULL_MSK BIT(2) 179 #define ADXL372_INT2_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2) 180 #define ADXL372_INT2_MAP_FIFO_OVR_MSK BIT(3) 181 #define ADXL372_INT2_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3) 182 #define ADXL372_INT2_MAP_INACT_MSK BIT(4) 183 #define ADXL372_INT2_MAP_INACT_MODE(x) (((x) & 0x1) << 4) 184 #define ADXL372_INT2_MAP_ACT_MSK BIT(5) 185 #define ADXL372_INT2_MAP_ACT_MODE(x) (((x) & 0x1) << 5) 186 #define ADXL372_INT2_MAP_AWAKE_MSK BIT(6) 187 #define ADXL372_INT2_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6) 188 #define ADXL372_INT2_MAP_LOW_MSK BIT(7) 189 #define ADXL372_INT2_MAP_LOW_MODE(x) (((x) & 0x1) << 7) 190 191 /* ADXL372_HPF */ 192 #define ADXL372_HPF_CORNER(x) (((x) & 0x3) << 0) 193 194 enum adxl372_axis { 195 ADXL372_X_AXIS, 196 ADXL372_Y_AXIS, 197 ADXL372_Z_AXIS 198 }; 199 200 enum adxl372_op_mode { 201 ADXL372_STANDBY, 202 ADXL372_WAKE_UP, 203 ADXL372_INSTANT_ON, 204 ADXL372_FULL_BW_MEASUREMENT 205 }; 206 207 enum adxl372_bandwidth { 208 ADXL372_BW_200HZ, 209 ADXL372_BW_400HZ, 210 ADXL372_BW_800HZ, 211 ADXL372_BW_1600HZ, 212 ADXL372_BW_3200HZ, 213 ADXL372_BW_LPF_DISABLED = 0xC, 214 }; 215 216 enum adxl372_hpf_corner { 217 ADXL372_HPF_CORNER_0, 218 ADXL372_HPF_CORNER_1, 219 ADXL372_HPF_CORNER_2, 220 ADXL372_HPF_CORNER_3, 221 ADXL372_HPF_DISABLED, 222 }; 223 224 enum adxl372_act_proc_mode { 225 ADXL372_DEFAULT, 226 ADXL372_LINKED, 227 ADXL372_LOOPED 228 }; 229 230 enum adxl372_odr { 231 ADXL372_ODR_400HZ, 232 ADXL372_ODR_800HZ, 233 ADXL372_ODR_1600HZ, 234 ADXL372_ODR_3200HZ, 235 ADXL372_ODR_6400HZ 236 }; 237 238 enum adxl372_instant_on_th_mode { 239 ADXL372_INSTANT_ON_LOW_TH, 240 ADXL372_INSTANT_ON_HIGH_TH 241 }; 242 243 enum adxl372_wakeup_rate { 244 ADXL372_WUR_52ms, 245 ADXL372_WUR_104ms, 246 ADXL372_WUR_208ms, 247 ADXL372_WUR_512ms, 248 ADXL372_WUR_2048ms, 249 ADXL372_WUR_4096ms, 250 ADXL372_WUR_8192ms, 251 ADXL372_WUR_24576ms 252 }; 253 254 enum adxl372_filter_settle { 255 ADXL372_FILTER_SETTLE_370, 256 ADXL372_FILTER_SETTLE_16 257 }; 258 259 enum adxl372_fifo_format { 260 ADXL372_XYZ_FIFO, 261 ADXL372_X_FIFO, 262 ADXL372_Y_FIFO, 263 ADXL372_XY_FIFO, 264 ADXL372_Z_FIFO, 265 ADXL372_XZ_FIFO, 266 ADXL372_YZ_FIFO, 267 ADXL372_XYZ_PEAK_FIFO, 268 }; 269 270 enum adxl372_fifo_mode { 271 ADXL372_FIFO_BYPASSED, 272 ADXL372_FIFO_STREAMED, 273 ADXL372_FIFO_TRIGGERED, 274 ADXL372_FIFO_OLD_SAVED 275 }; 276 277 struct adxl372_fifo_config { 278 enum adxl372_fifo_mode fifo_mode; 279 enum adxl372_fifo_format fifo_format; 280 uint16_t fifo_samples; 281 }; 282 283 struct adxl372_activity_threshold { 284 uint16_t thresh; 285 bool referenced; 286 bool enable; 287 }; 288 289 struct adxl372_xyz_accel_data { 290 #ifdef CONFIG_ADXL372_STREAM 291 uint8_t is_fifo: 1; 292 uint8_t res: 7; 293 #endif /* CONFIG_ADXL372_STREAM */ 294 int16_t x; 295 int16_t y; 296 int16_t z; 297 }; 298 299 struct adxl372_transfer_function { 300 int (*read_reg_multiple)(const struct device *dev, uint8_t reg_addr, 301 uint8_t *value, uint16_t len); 302 int (*write_reg)(const struct device *dev, uint8_t reg_addr, 303 uint8_t value); 304 int (*read_reg)(const struct device *dev, uint8_t reg_addr, 305 uint8_t *value); 306 int (*write_reg_mask)(const struct device *dev, uint8_t reg_addr, 307 uint32_t mask, uint8_t value); 308 }; 309 310 struct adxl372_data { 311 struct adxl372_xyz_accel_data sample; 312 const struct adxl372_transfer_function *hw_tf; 313 struct adxl372_fifo_config fifo_config; 314 enum adxl372_act_proc_mode act_proc_mode; 315 #ifdef CONFIG_ADXL372_TRIGGER 316 struct gpio_callback gpio_cb; 317 318 sensor_trigger_handler_t th_handler; 319 const struct sensor_trigger *th_trigger; 320 sensor_trigger_handler_t drdy_handler; 321 const struct sensor_trigger *drdy_trigger; 322 const struct device *dev; 323 324 #if defined(CONFIG_ADXL372_TRIGGER_OWN_THREAD) 325 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL372_THREAD_STACK_SIZE); 326 struct k_sem gpio_sem; 327 struct k_thread thread; 328 #elif defined(CONFIG_ADXL372_TRIGGER_GLOBAL_THREAD) 329 struct k_work work; 330 #endif 331 #endif /* CONFIG_ADXL372_TRIGGER */ 332 #ifdef CONFIG_ADXL372_STREAM 333 struct rtio_iodev_sqe *sqe; 334 struct rtio *rtio_ctx; 335 struct rtio_iodev *iodev; 336 uint8_t status1; 337 uint8_t fifo_ent[2]; 338 uint64_t timestamp; 339 uint8_t fifo_full_irq; 340 uint8_t pwr_reg; 341 #endif /* CONFIG_ADXL372_STREAM */ 342 }; 343 344 struct adxl372_dev_config { 345 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 346 struct i2c_dt_spec i2c; 347 #endif 348 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 349 struct spi_dt_spec spi; 350 #endif 351 int (*bus_init)(const struct device *dev); 352 #ifdef CONFIG_ADXL372_TRIGGER 353 struct gpio_dt_spec interrupt; 354 #endif 355 356 enum adxl372_bandwidth bw; 357 enum adxl372_hpf_corner hpf; 358 enum adxl372_odr odr; 359 360 bool max_peak_detect_mode; 361 362 /* Device Settings */ 363 bool autosleep; 364 365 struct adxl372_activity_threshold activity_th; 366 struct adxl372_activity_threshold activity2_th; 367 struct adxl372_activity_threshold inactivity_th; 368 struct adxl372_fifo_config fifo_config; 369 370 enum adxl372_wakeup_rate wur; 371 enum adxl372_instant_on_th_mode th_mode; 372 enum adxl372_filter_settle filter_settle; 373 enum adxl372_op_mode op_mode; 374 375 uint16_t inactivity_time; 376 uint8_t activity_time; 377 uint8_t int1_config; 378 uint8_t int2_config; 379 }; 380 381 struct adxl372_fifo_data { 382 uint8_t is_fifo: 1; 383 uint8_t sample_set_size: 4; 384 uint8_t has_x: 1; 385 uint8_t has_y: 1; 386 uint8_t has_z: 1; 387 uint8_t int_status; 388 uint16_t accel_odr: 4; 389 uint16_t fifo_byte_count: 12; 390 uint64_t timestamp; 391 } __attribute__((__packed__)); 392 393 BUILD_ASSERT(sizeof(struct adxl372_fifo_data) % 4 == 0, 394 "adxl372_fifo_data struct should be word aligned"); 395 396 int adxl372_spi_init(const struct device *dev); 397 int adxl372_i2c_init(const struct device *dev); 398 399 void adxl372_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 400 void adxl372_stream_irq_handler(const struct device *dev); 401 402 #ifdef CONFIG_ADXL372_TRIGGER 403 int adxl372_get_status(const struct device *dev, 404 uint8_t *status1, uint8_t *status2, uint16_t *fifo_entries); 405 406 int adxl372_trigger_set(const struct device *dev, 407 const struct sensor_trigger *trig, 408 sensor_trigger_handler_t handler); 409 410 int adxl372_init_interrupt(const struct device *dev); 411 #endif /* CONFIG_ADXL372_TRIGGER */ 412 413 #ifdef CONFIG_SENSOR_ASYNC_API 414 int adxl372_get_accel_data(const struct device *dev, bool maxpeak, 415 struct adxl372_xyz_accel_data *accel_data); 416 void adxl372_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 417 int adxl372_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); 418 void adxl372_accel_convert(struct sensor_value *val, int16_t sample); 419 #endif /* CONFIG_SENSOR_ASYNC_API */ 420 421 #ifdef CONFIG_ADXL372_STREAM 422 int adxl372_configure_fifo(const struct device *dev, enum adxl372_fifo_mode mode, 423 enum adxl372_fifo_format format, uint16_t fifo_samples); 424 size_t adxl372_get_packet_size(const struct adxl372_dev_config *cfg); 425 int adxl372_set_op_mode(const struct device *dev, enum adxl372_op_mode op_mode); 426 #endif /* CONFIG_ADXL372_STREAM */ 427 428 #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ */ 429
