1 /*
2  * Copyright (c) 2021 Katsuhiro Suzuki
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _SIFIVE_FU740_PRCI_H
8 #define _SIFIVE_FU740_PRCI_H
9 
10 /* Clock controller. */
11 #define PRCI_BASE_ADDR 0x10000000UL
12 
13 #define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
14 #define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset)
15 
16 /* Register offsets */
17 
18 #define PRCI_HFXOSCCFG          (0x0000)
19 #define PRCI_COREPLLCFG         (0x0004)
20 #define PRCI_COREPLLOUTDIV      (0x0008)
21 #define PRCI_DDRPLLCFG          (0x000c)
22 #define PRCI_DDRPLLOUTDIV       (0x0010)
23 #define PRCI_GEMGXLPLLCFG       (0x001c)
24 #define PRCI_GEMGXLPLLOUTDIV    (0x0020)
25 #define PRCI_CORECLKSEL         (0x0024)
26 #define PRCI_DEVICESRESETN      (0x0028)
27 #define PRCI_CLKMUXSTATUS       (0x002c)
28 #define PRCI_COREPLLSEL         (0x0040)
29 #define PRCI_HFPCLKPLLCFG       (0x0050)
30 #define PRCI_HFPCLKPLLOUTDIV    (0x0054)
31 #define PRCI_HFPCLKPLLSEL       (0x0058)
32 
33 #define PLL_R(x)       (((x) & 0x3f)  << 0)
34 #define PLL_F(x)       (((x) & 0x1ff) << 6)
35 #define PLL_Q(x)       (((x) & 0x7)   << 15)
36 #define PLL_RANGE(x)   (((x) & 0x7)   << 18)
37 #define PLL_BYPASS(x)  (((x) & 0x1)   << 24)
38 #define PLL_FSE(x)     (((x) & 0x1)   << 25)
39 #define PLL_LOCK(x)    (((x) & 0x1)   << 31)
40 
41 #define PLL_RANGE_RESET        0
42 #define PLL_RANGE_0MHZ         1
43 #define PLL_RANGE_11MHZ        2
44 #define PLL_RANGE_18MHZ        3
45 #define PLL_RANGE_30MHZ        4
46 #define PLL_RANGE_50MHZ        5
47 #define PLL_RANGE_80MHZ        6
48 #define PLL_RANGE_130MHZ       7
49 #define PLL_BYPASS_DISABLE     0
50 #define PLL_BYPASS_ENABLE      1
51 #define PLL_FSE_INTERNAL       1
52 
53 #define OUTDIV_PLLCKE(x)    (((x) & 0x1) << 31)
54 
55 #define OUTDIV_PLLCKE_DIS    0
56 #define OUTDIV_PLLCKE_ENA    1
57 
58 #define CLKSEL_SEL(x)    (((x) & 0x1)  << 0)
59 
60 #define CLKSEL_PLL      0
61 #define CLKSEL_HFCLK    1
62 
63 #define CLKMUXSTATUS_CORECLKPLLSEL_OFF    0
64 #define CLKMUXSTATUS_TLCLKSEL_OFF         1
65 #define CLKMUXSTATUS_RTCXSEL_OFF          2
66 #define CLKMUXSTATUS_DDRCTRLCLKSEL_OFF    3
67 #define CLKMUXSTATUS_DDRPHYCLKSEL_OFF     4
68 #define CLKMUXSTATUS_GEMGXLCLKSEL_OFF     6
69 #define CLKMUXSTATUS_MAINMEMCLKSEL_OFF    7
70 
71 #define COREPLLSEL_SEL(x)    (((x) & 0x1)  << 0)
72 
73 #define COREPLLSEL_COREPLL        0
74 #define COREPLLSEL_DVFSCOREPLL    1
75 
76 #define DEVICERESETN_DDRCTRL BIT(0)
77 #define DEVICERESETN_DDRAXI  BIT(1)
78 #define DEVICERESETN_DDRAHB  BIT(2)
79 #define DEVICERESETN_DDRPHY  BIT(3)
80 #define DEVICERESETN_PCIEAUX BIT(4)
81 #define DEVICERESETN_GEMGXL  BIT(5)
82 
83 #endif /* _SIFIVE_FU740_PRCI_H */
84