| /Zephyr-latest/tests/drivers/pinctrl/gd32/src/ |
| D | main_afio.c | 9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ANALOG); in ZTEST()
30 zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP); in ZTEST()
32 pin = scfg->pins[1]; in ZTEST()
33 zassert_equal(GD32_PORT_GET(pin), 1); in ZTEST()
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| D | main_af.c | 9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_AF_GET(pin), GD32_AF0); in ZTEST()
30 zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE); in ZTEST()
31 zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP); in ZTEST()
32 zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ); in ZTEST()
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| /Zephyr-latest/tests/drivers/sensor/adltc2990/boards/ |
| D | native_sim.overlay | 7 adltc2990_0_0: adltc2990_0_0@1 {
13 pin-v1-voltage-divider-resistors = <500 1000>;
14 pin-v2-voltage-divider-resistors = <110000 100000>;
15 pin-v3-voltage-divider-resistors = <7000 1000>;
16 pin-v4-voltage-divider-resistors = <500 1000>;
23 acquistion-format = <1>;
24 measurement-mode = <1 3>;
27 pin-v1-voltage-divider-resistors = <0 1>;
28 pin-v2-voltage-divider-resistors = <0 1>;
29 pin-v3-voltage-divider-resistors = <0 1>;
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_gpio.h | 19 * Pin flags/attributes
22 /* TODO: replace hard coded pin attribute values with defines provided
31 #define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS)
32 #define SOC_GPIO_PULLDOWN_POS (1)
33 #define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS)
35 #define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS)
41 #define SOC_GPIO_IN_FILTER_DEBOUNCE (1 << SOC_GPIO_IN_FILTER_POS)
44 #define SOC_GPIO_INT_ENABLE (1 << 5)
52 #define SOC_GPIO_INT_TRIG_EDGE (1 << SOC_GPIO_INT_TRIG_POS)
57 #define SOC_GPIO_INT_ACTIVE_HIGH (1 << 8)
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| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | soc_port.h | 8 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
17 * Pin flags/attributes
24 #define SOC_PORT_PULLUP (1 << SOC_PORT_PULLUP_POS)
25 #define SOC_PORT_PULLDOWN_POS (SOC_PORT_PULLUP_POS + 1U)
26 #define SOC_PORT_PULLDOWN (1 << SOC_PORT_PULLDOWN_POS)
28 #define SOC_GPIO_OPENDRAIN_POS (SOC_PORT_PULLDOWN_POS + 1U)
30 #define SOC_PORT_INPUT_ENABLE_POS (SOC_GPIO_OPENDRAIN_POS + 1U)
31 #define SOC_PORT_INPUT_ENABLE (1 << SOC_PORT_INPUT_ENABLE_POS)
33 #define SOC_PORT_OUTPUT_ENABLE_POS (SOC_PORT_INPUT_ENABLE_POS + 1U)
34 #define SOC_PORT_OUTPUT_ENABLE (1 << SOC_PORT_OUTPUT_ENABLE_POS)
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| D | soc_port.c | 9 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
16 int soc_port_pinmux_set(PortGroup *pg, uint32_t pin, uint32_t func) in soc_port_pinmux_set() argument
18 bool is_odd = pin & 1; in soc_port_pinmux_set()
19 int idx = pin / 2U; in soc_port_pinmux_set()
22 * even numbered pin goes in the bits 0..3 and the odd in soc_port_pinmux_set()
23 * numbered pin in bits 4..7. in soc_port_pinmux_set()
30 pg->PINCFG[pin].bit.PMUXEN = 1; in soc_port_pinmux_set()
35 void soc_port_configure(const struct soc_port_pin *pin) in soc_port_configure() argument
37 PortGroup *pg = pin->regs; in soc_port_configure()
38 uint32_t flags = pin->flags; in soc_port_configure()
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| /Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/src/ |
| D | test_config.c | 16 unsigned int pin, in pin_get_raw_and_verify() argument
21 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
23 "Test point %d: failed to get pin value", idx); in pin_get_raw_and_verify()
25 "Test point %d: invalid pin get value", idx); in pin_get_raw_and_verify()
29 unsigned int pin, in pin_set_raw_and_verify() argument
32 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
33 "Test point %d: failed to set pin value", idx); in pin_set_raw_and_verify()
39 * - Configure pin in in/out mode, verify that gpio_pin_set_raw /
40 * gpio_pin_get_raw operations change pin state.
41 * - Verify that GPIO_OUTPUT_HIGH flag is initializing the pin to high.
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| D | test_pin_interrupt.c | 20 "Detected interrupt on an invalid pin"); in callback_edge()
31 "Detected interrupt on an invalid pin"); in callback_level()
37 "Failed to disable pin interrupt in the callback"); in callback_level()
41 static void pin_set_and_verify(const struct device *port, unsigned int pin, in pin_set_and_verify() argument
45 zassert_equal(gpio_pin_set(port, pin, val), 0, in pin_set_and_verify()
46 "Test point %d: failed to set logical pin value", idx); in pin_set_and_verify()
61 TC_PRINT("Running test on port=%s, pin=%d\n", port->name, TEST_PIN); in test_gpio_pin_interrupt_edge()
65 TC_PRINT("Simultaneous pin in/out mode is not supported.\n"); in test_gpio_pin_interrupt_edge()
69 zassert_equal(ret, 0, "Failed to configure the pin"); in test_gpio_pin_interrupt_edge()
78 zassert_equal(ret, 0, "Failed to configure the pin"); in test_gpio_pin_interrupt_edge()
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| D | test_pin.c | 13 unsigned int pin, in pin_get_raw_and_verify() argument
18 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
20 "Test point %d: failed to get physical pin value", idx); in pin_get_raw_and_verify()
22 "Test point %d: invalid physical pin get value", idx); in pin_get_raw_and_verify()
25 static void pin_get_and_verify(const struct device *port, unsigned int pin, in pin_get_and_verify() argument
30 val_actual = gpio_pin_get(port, pin); in pin_get_and_verify()
32 "Test point %d: failed to get logical pin value", idx); in pin_get_and_verify()
34 "Test point %d: invalid logical pin get value", idx); in pin_get_and_verify()
38 unsigned int pin, in pin_set_raw_and_verify() argument
41 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,rt-iocon-pinctrl.yaml | 5 RT600/RT500 pin control node. This node defines pin configurations in pin
7 group within the pin configuration defines a peripheral's pin configuration.
24 IOCON_FUNC=<pin mux selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
38 input-enable: IOCON_IBENA=1
45 description: iMX RT IOCON pin controller pin group
48 iMX RT IOCON pin controller pin configuration node
63 Pin mux selection for this group. See the SOC level pinctrl header
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| D | ambiq,apollo4-pinctrl.yaml | 5 The Ambiq Apollo4 pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a UART0 TX
7 to pin 60 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
38 The 'uart0_default' child node encodes the pin configurations for a
42 As shown, pin configurations are organized in groups within each child node.
43 Each group can specify a list of pin function selections in the 'pinmux'
46 A group can also specify shared pin properties common to all the specified
75 pin number and the alternative function of the pin.
85 The drive strength of a pin, relative to full-driver strength.
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| D | raspberrypi,pico-pinctrl.yaml | 6 The RPi Pico pin controller is a node responsible for controlling
7 pin function selection and pin properties, such as routing a UART0 Rx
8 to pin 1 and enabling the pullup resistor on that pin.
17 All device pin configurations should be placed in child nodes of the
30 /* group 1 */
39 /* enable input on pin 1 */
45 The 'uart0_default' child node encodes the pin configurations for a
49 As shown, pin configurations are organized in groups within each child node.
50 Each group can specify a list of pin function selections in the 'pinmux'
53 A group can also specify shared pin properties common to all the specified
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| D | nxp,lpc-iocon-pinctrl.yaml | 5 LPC pinctrl node. This node defines pin configurations in pin groups, and has
7 pin configuration defines a peripheral's pin configuration. Each numbered
22 IOCON_FUNC=<pin mux selection>,
26 IOCON_DIGIMODE=1,
32 IOCON_FILTEROFF=1
34 IOCON_EGP=1
35 IOCON_I2CFILTER=1
38 drive-open-drain: IOCON_OD=1
40 bias-pull-down: IOCON_MODE=1
55 description: LPC IOCON pin controller pin group
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| D | adi,max32-pinctrl.yaml | 5 MAX32 Pin controller Node
8 Note: `bias-disable` are default pin configurations.
41 Integer array, represents gpio pin number and mux setting.
42 These defines are calculated as: (pin<<8 | port<<4 | function<<0)
44 - port: The gpio port index (0, 1, ...)
45 - pin: The pin offset within the port (0, 1, 2, ...)
48 * 1 : Alternate Function 1
52 In case selected pin function is GPIO, pin is statically configured as
55 to the pin configuration.
61 P0.9 set as alernate function 1
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| D | nordic,nrf-pinctrl.yaml | 5 The nRF pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
8 pin.
17 All device pin configurations should be placed in child nodes of the
26 /* group 1 ('group1' name is arbitrary) */
28 /* configure P0.1 as UART_TX and P0.2 as UART_RTS */
29 psels = <NRF_PSEL(UART_TX, 0, 1)>, <NRF_PSEL(UART_RTS, 0, 2)>;
41 The 'uart0_default' child node encodes the pin configurations for a
46 As shown, pin configurations are organized in groups within each child node.
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| D | silabs,gecko-pinctrl.yaml | 5 The Silabs pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
8 pin.
17 All device pin configurations should be placed in child nodes of the
26 /* group 1 ('group1' name is arbitrary) */
28 /* configure P0.1 as UART_TX and P0.2 as UART_RTS */
29 psels = <GECKO_PSEL(UART_TX, A, 1)>, <GECKO_PSEL(UART_RTS, A, 2)>;
39 The 'usart0_default' child node encodes the pin configurations for a
44 As shown, pin configurations are organized in groups within each child node.
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| D | nxp,mcux-rt11xx-pinctrl.yaml | 25 drive-open-drain: ODE/ODE_LPSR=1
26 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
27 bias-pull-down: PUE=1, PUS=0
28 bias-pull-up: PUE=1, PUS=1
33 If only required properties are supplied, the pin will have the following
52 description: MCUX RT pin controller pin group
55 MCUX RT pin controller pin configuration node.
71 Pin mux selections for this group. See the soc level iomuxc DTSI file
79 Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
80 0 (normal) - sets pin to normal drive strength
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_eos_s3.c | 34 static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg) in pinctrl_eos_s3_input_selection() argument
42 *reg = pin; in pinctrl_eos_s3_input_selection()
50 static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func) in pinctrl_eos_s3_set() argument
54 if (pin > IO_MUX_REG_MAX_OFFSET) { in pinctrl_eos_s3_set()
57 reg += pin; in pinctrl_eos_s3_set()
63 static int pinctrl_eos_s3_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_eos_s3_configure_pin() argument
68 reg_value |= (pin->iof & PAD_FUNC_SEL_MASK); in pinctrl_eos_s3_configure_pin()
71 WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1); in pinctrl_eos_s3_configure_pin()
74 WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable); in pinctrl_eos_s3_configure_pin()
75 WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate); in pinctrl_eos_s3_configure_pin()
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| D | pinctrl_wch_afio.c | 24 uint8_t pin = (pins->config >> CH32V003_PINCTRL_PIN_SHIFT) & 0x0F; in pinctrl_configure_pins() local
36 cfg |= (pins->slew_rate + 1); in pinctrl_configure_pins()
47 regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4)); in pinctrl_configure_pins()
50 regs->OUTDR |= BIT(pin); in pinctrl_configure_pins()
51 regs->BSHR |= BIT(pin); in pinctrl_configure_pins()
53 regs->OUTDR |= BIT(pin); in pinctrl_configure_pins()
54 /* Reset the pin. */ in pinctrl_configure_pins()
55 regs->BSHR |= BIT(pin + 16); in pinctrl_configure_pins()
57 regs->OUTDR &= ~(1 << pin); in pinctrl_configure_pins()
59 regs->BSHR = BIT(pin); in pinctrl_configure_pins()
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_ene_kb1200.c | 40 static int kb1200_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in kb1200_gpio_pin_configure() argument
44 WRITE_BIT(config->gpio_regs->GPIOFS, pin, 0); in kb1200_gpio_pin_configure()
46 WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1); in kb1200_gpio_pin_configure()
49 WRITE_BIT(config->gpio_regs->GPIOOD, pin, 1); in kb1200_gpio_pin_configure()
52 WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0); in kb1200_gpio_pin_configure()
55 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1); in kb1200_gpio_pin_configure()
57 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0); in kb1200_gpio_pin_configure()
60 WRITE_BIT(config->gpio_regs->GPIOD, pin, 1); in kb1200_gpio_pin_configure()
62 WRITE_BIT(config->gpio_regs->GPIOD, pin, 0); in kb1200_gpio_pin_configure()
64 WRITE_BIT(config->gpio_regs->GPIOOE, pin, 1); in kb1200_gpio_pin_configure()
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| /Zephyr-latest/soc/silabs/silabs_sim3/sim3u/ |
| D | gen_crossbar_config.py | 18 - crossbar 0: Controls portbanks 0 and 1
19 - crossbar 1: Controls portbanks 2 and 3
28 - pbskipen: A bitmask where value `1` means, that the pin will not be muxed.
29 The index of the bit refers to the pin number.
34 available pin. That has a few implications:
37 - Peripherals that appear first in the signal list will always use lower pin-numbers than later ones
59 USART0_RX = 1
78 DIGITAL_INPUT = 1
84 self.pin = (value & 0x7, (value >> 3) & 0xFF)
153 for pin in pins:
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| /Zephyr-latest/samples/drivers/clock_control_xec/ |
| D | README.rst | 20 GPIO221 alternate function 1 is 32KHZ_OUT and can be monitored on Assembly 6915 JP7 pin 5.
25 JP1 pin 2 to GND (ground MEC172x XTAL1 pin)
31 Jumper on JP1 1-2 connect crystal Y1 pin 1 to MEC172x XTAL1
32 Jumper on JP2 2-3 connect crystal Y1 pin 2 to MEC172x XTAL2
42 JP1 pin 2 to GND (ground MEC172x XTAL1 pin)
43 Jumper on JP2 1-2 connect external 32KHz signal to XTAL2
48 XTAL2_32KHZ_IN signal routed to XTAL2 MEC172x pin on Assembly 6915
50 External single-ended 32KHz waveform to MEC172x 32KHZ_IN pin
53 JP1 pin 2 to GND (ground MEC172x XTAL1 pin)
58 Jumper on JP121 pins 1-2 connect U15 32KHz output to
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| /Zephyr-latest/dts/bindings/power/ |
| D | st,stm32-pwr.yaml | 20 wkup-pin-srcs:
23 Number of wake-up GPIO sources to select from for each wake-up pin.
24 If not specified, that means there is only 1 GPIO source for each
25 wake-up pin.
27 For example, each wake-up pin on STM32U5 is associated with
42 const: 1
49 STM32 wake-up pin node.
51 All nodes using this binding must be named "wkup-pin@[index]"
52 index starts from 1
58 description: Wake-up pin identifier, same as "index" in node name
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| /Zephyr-latest/drivers/pinctrl/renesas/rz/ |
| D | pinctrl_rzt2m.c | 21 #define DRCTL(port, pin) (PORT_NSR + 0xa00 + (0x8 * port) + pin) argument
32 #define PFC_FUNC_MASK(pin) (0xf << (pin * 4)) argument
34 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
36 uint8_t rselp = sys_read8(RSELP(pin->port)); in pinctrl_configure_pin()
37 uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin)); in pinctrl_configure_pin()
38 uint8_t pmc = sys_read8(PMC(pin->port)); in pinctrl_configure_pin()
41 sys_write8(rselp | BIT(pin->pin), RSELP(pin->port)); in pinctrl_configure_pin()
43 pin->drive_strength, (pin->pull_up == 1 ? 1U : (pin->pull_down == 1 ? 2U : 0)), in pinctrl_configure_pin()
44 pin->schmitt_enable, pin->slew_rate), in pinctrl_configure_pin()
45 DRCTL(pin->port, pin->pin)); in pinctrl_configure_pin()
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | cc13xx_cc26xx-pinctrl.h | 15 #define IOC_PORT_AUX_IO 0x00000008 /* AUX IO Pin */
16 #define IOC_PORT_MCU_SSI0_RX 0x00000009 /* MCU SSI0 Receive Pin */
17 #define IOC_PORT_MCU_SSI0_TX 0x0000000A /* MCU SSI0 Transmit Pin */
18 #define IOC_PORT_MCU_SSI0_FSS 0x0000000B /* MCU SSI0 FSS Pin */
19 #define IOC_PORT_MCU_SSI0_CLK 0x0000000C /* MCU SSI0 Clock Pin */
20 #define IOC_PORT_MCU_I2C_MSSDA 0x0000000D /* MCU I2C Data Pin */
21 #define IOC_PORT_MCU_I2C_MSSCL 0x0000000E /* MCU I2C Clock Pin */
22 #define IOC_PORT_MCU_UART0_RX 0x0000000F /* MCU UART0 Receive Pin */
23 #define IOC_PORT_MCU_UART0_TX 0x00000010 /* MCU UART0 Transmit Pin */
24 #define IOC_PORT_MCU_UART0_CTS 0x00000011 /* MCU UART0 Clear To Send Pin */
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