Lines Matching +full:1 +full:pin

25   drive-open-drain: ODE/ODE_LPSR=1
26   input-enable: SION=1 (in SW_MUX_CTL_PAD register)
27   bias-pull-down: PUE=1, PUS=0
28   bias-pull-up: PUE=1, PUS=1
33   If only required properties are supplied, the pin will have the following
52   description: MCUX RT pin controller pin group
55       MCUX RT pin controller pin configuration node.
71           Pin mux selections for this group. See the soc level iomuxc DTSI file
79           Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
80           0 (normal) - sets pin to normal drive strength
81           1 (high) - sets pin to high drive strength
88           Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
90           1 (slow) — Slow Slew Rate