Lines Matching +full:1 +full:pin

18 - crossbar 0: Controls portbanks 0 and 1
19 - crossbar 1: Controls portbanks 2 and 3
28 - pbskipen: A bitmask where value `1` means, that the pin will not be muxed.
29             The index of the bit refers to the pin number.
34 available pin. That has a few implications:
37 - Peripherals that appear first in the signal list will always use lower pin-numbers than later ones
59     USART0_RX = 1
78     DIGITAL_INPUT = 1
84         self.pin = (value & 0x7, (value >> 3) & 0xFF)
153         for pin in pins:
154             if pin < self.first_configurable:
156                     "can't enable crossbar pin anymore", pin, self.first_configurable
159             self.portbanks[pin[0]].unskip(pin[1])
161             self.first_configurable = (pin[0], pin[1] + 1)
163         self.value |= 1 << bit.bit
170                 if self.number == 0 and mux.pin[0] != 0 and mux.pin[0] != 1:
172                 if self.number == 1 and mux.pin[0] != 2 and mux.pin[0] != 3:
179                 if mux.pin < bit.pin_first or mux.pin > bit.pin_last:
180                     raise Exception("can't mux signal to pin", mux, bit)
191             # build pin list for this bit in the required order
195                 pins.append(mux.pin)
200                 self.portbanks[mux.pin[0]].apply_mux(mux.pin[1], mux)
217     def unskip(self, pin):  argument
218         self.skip_enable &= ~(1 << pin)
220     def apply_mux(self, pin, mux):  argument
222             self.pins_analog |= 1 << pin
224             self.pins_digital_input |= 1 << pin
226             self.pins_push_pull_output |= 1 << pin
229                 self.pins_high |= 1 << pin
231                 self.pins_low |= 1 << pin
272                 for pin in child.props["pinmux"].val:
273                     pinmux_table.append(Pinmux(pin, child.props))
276         CrossbarBit(0, [Signal.USART0_TX, Signal.USART0_RX], (0, 0), (1, 15)),
277         CrossbarBit(1, [Signal.USART0_RTS, Signal.USART0_CTS], (0, 0), (1, 15)),
278         CrossbarBit(2, [Signal.USART0_UCLK], (0, 0), (1, 15)),
279         CrossbarBit(5, [Signal.USART1_TX, Signal.USART1_RX], (0, 0), (1, 15)),
280         CrossbarBit(6, [Signal.USART1_RTS, Signal.USART1_CTS], (0, 0), (1, 15)),
281         CrossbarBit(7, [Signal.USART1_UCLK], (0, 0), (1, 15)),
286             (1, 15),
288         CrossbarBit(32 + 4, [Signal.SPI2_NSS], (0, 0), (1, 15)),
300         Crossbar(1, crossbar1_bits, portbanks),