1 /*
2 * Copyright (c) 2023 ENE Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ene_kb1200_gpio
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/kernel.h>
11 #include <zephyr/drivers/gpio/gpio_utils.h>
12 #include <zephyr/sys/util_macro.h>
13 #include <reg/gpio.h>
14 #include <reg/gptd.h>
15
16 struct gpio_kb1200_data {
17 /* gpio_driver_data needs to be first */
18 struct gpio_driver_data common;
19 sys_slist_t cb;
20 };
21
22 struct gpio_kb1200_config {
23 /* gpio_driver_config needs to be first */
24 struct gpio_driver_config common;
25 /* base address of GPIO port */
26 struct gpio_regs *gpio_regs;
27 struct gptd_regs *gptd_regs;
28 };
29
gpio_kb1200_isr(const struct device * dev)30 static void gpio_kb1200_isr(const struct device *dev)
31 {
32 const struct gpio_kb1200_config *config = dev->config;
33 struct gpio_kb1200_data *context = dev->data;
34 uint32_t pending_flag = config->gptd_regs->GPTDPF;
35
36 gpio_fire_callbacks(&context->cb, dev, pending_flag);
37 config->gptd_regs->GPTDPF |= pending_flag;
38 }
39
kb1200_gpio_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)40 static int kb1200_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
41 {
42 const struct gpio_kb1200_config *config = dev->config;
43
44 WRITE_BIT(config->gpio_regs->GPIOFS, pin, 0);
45 if ((flags & GPIO_OUTPUT) != 0) {
46 WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1);
47 if ((flags & GPIO_SINGLE_ENDED) != 0) {
48 if (flags & GPIO_LINE_OPEN_DRAIN) {
49 WRITE_BIT(config->gpio_regs->GPIOOD, pin, 1);
50 }
51 } else {
52 WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0);
53 }
54 if (flags & GPIO_PULL_UP) {
55 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1);
56 } else {
57 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0);
58 }
59 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
60 WRITE_BIT(config->gpio_regs->GPIOD, pin, 1);
61 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
62 WRITE_BIT(config->gpio_regs->GPIOD, pin, 0);
63 }
64 WRITE_BIT(config->gpio_regs->GPIOOE, pin, 1);
65 } else {
66 WRITE_BIT(config->gpio_regs->GPIOOE, pin, 0);
67 if (flags & GPIO_PULL_UP) {
68 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1);
69 } else {
70 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0);
71 }
72 WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1);
73 }
74 return 0;
75 }
76
kb1200_gpio_port_get_raw(const struct device * dev,gpio_port_value_t * value)77 static int kb1200_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value)
78 {
79 const struct gpio_kb1200_config *config = dev->config;
80
81 *value = config->gpio_regs->GPIOIN;
82 return 0;
83 }
84
kb1200_gpio_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)85 static int kb1200_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
86 gpio_port_value_t value)
87 {
88 const struct gpio_kb1200_config *config = dev->config;
89
90 config->gpio_regs->GPIOD |= (value & mask);
91 return 0;
92 }
93
kb1200_gpio_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)94 static int kb1200_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
95 {
96 const struct gpio_kb1200_config *config = dev->config;
97
98 config->gpio_regs->GPIOD |= pins;
99 return 0;
100 }
101
kb1200_gpio_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)102 static int kb1200_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
103 {
104 const struct gpio_kb1200_config *config = dev->config;
105
106 config->gpio_regs->GPIOD &= ~pins;
107 return 0;
108 }
109
kb1200_gpio_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)110 static int kb1200_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
111 {
112 const struct gpio_kb1200_config *config = dev->config;
113
114 config->gpio_regs->GPIOD ^= pins;
115 return 0;
116 }
117
kb1200_gpio_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)118 static int kb1200_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
119 enum gpio_int_mode mode, enum gpio_int_trig trig)
120 {
121 const struct gpio_kb1200_config *config = dev->config;
122
123 /* Check if GPIO port needs interrupt support */
124 if ((mode & GPIO_INT_DISABLE) || (mode & GPIO_INT_ENABLE) == 0) {
125 /* Set the mask to disable the interrupt */
126 WRITE_BIT(config->gptd_regs->GPTDIE, pin, 0);
127 } else {
128 if (mode & GPIO_INT_EDGE) {
129 WRITE_BIT(config->gptd_regs->GPTDEL, pin, 0);
130 if (trig & GPIO_INT_HIGH_1) {
131 if (trig & GPIO_INT_LOW_0) { /* Falling & Rising edge trigger */
132 /* Enable toggle trigger */
133 WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 1);
134 } else { /* Rising edge */
135 /* Disable toggle trigger */
136 WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0);
137 WRITE_BIT(config->gptd_regs->GPTDPS, pin, 1);
138 }
139 } else { /* Falling edge */
140 /* Disable Toggle trigger */
141 WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0);
142 WRITE_BIT(config->gptd_regs->GPTDPS, pin, 0);
143 }
144 } else {
145 WRITE_BIT(config->gptd_regs->GPTDEL, pin, 1);
146 /* Disable Toggle trigger */
147 WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0);
148 if (trig & GPIO_INT_HIGH_1) {
149 WRITE_BIT(config->gptd_regs->GPTDPS, pin, 1);
150 } else {
151 WRITE_BIT(config->gptd_regs->GPTDPS, pin, 0);
152 }
153 }
154 /* clear pending flag */
155 WRITE_BIT(config->gptd_regs->GPTDPF, pin, 1);
156 /* Enable the interrupt */
157 WRITE_BIT(config->gptd_regs->GPTDIE, pin, 1);
158 }
159 return 0;
160 }
161
kb1200_gpio_manage_callback(const struct device * dev,struct gpio_callback * cb,bool set)162 static int kb1200_gpio_manage_callback(const struct device *dev, struct gpio_callback *cb, bool set)
163 {
164 struct gpio_kb1200_data *context = dev->data;
165
166 gpio_manage_callback(&context->cb, cb, set);
167 return 0;
168 }
169
kb1200_gpio_get_pending_int(const struct device * dev)170 static uint32_t kb1200_gpio_get_pending_int(const struct device *dev)
171 {
172 const struct gpio_kb1200_config *const config = dev->config;
173
174 return config->gptd_regs->GPTDPF;
175 }
176
177 static DEVICE_API(gpio, kb1200_gpio_api) = {
178 .pin_configure = kb1200_gpio_pin_configure,
179 .port_get_raw = kb1200_gpio_port_get_raw,
180 .port_set_masked_raw = kb1200_gpio_port_set_masked_raw,
181 .port_set_bits_raw = kb1200_gpio_port_set_bits_raw,
182 .port_clear_bits_raw = kb1200_gpio_port_clear_bits_raw,
183 .port_toggle_bits = kb1200_gpio_port_toggle_bits,
184 .pin_interrupt_configure = kb1200_gpio_pin_interrupt_configure,
185 .manage_callback = kb1200_gpio_manage_callback,
186 .get_pending_int = kb1200_gpio_get_pending_int,
187 };
188
189 #define KB1200_GPIO_INIT(n) \
190 static int kb1200_gpio_##n##_init(const struct device *dev) \
191 { \
192 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), DT_INST_IRQ_BY_IDX(n, 0, priority), \
193 gpio_kb1200_isr, DEVICE_DT_INST_GET(n), 0); \
194 irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \
195 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), DT_INST_IRQ_BY_IDX(n, 1, priority), \
196 gpio_kb1200_isr, DEVICE_DT_INST_GET(n), 0); \
197 irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \
198 return 0; \
199 }; \
200 static const struct gpio_kb1200_config port_##n##_kb1200_config = { \
201 .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n)}, \
202 .gpio_regs = (struct gpio_regs *)DT_INST_REG_ADDR_BY_IDX(n, 0), \
203 .gptd_regs = (struct gptd_regs *)DT_INST_REG_ADDR_BY_IDX(n, 1), \
204 }; \
205 static struct gpio_kb1200_data gpio_kb1200_##n##_data; \
206 DEVICE_DT_INST_DEFINE(n, &kb1200_gpio_##n##_init, NULL, &gpio_kb1200_##n##_data, \
207 &port_##n##_kb1200_config, POST_KERNEL, \
208 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &kb1200_gpio_api);
209
210 DT_INST_FOREACH_STATUS_OKAY(KB1200_GPIO_INIT)
211
