| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcx-pcc.yaml | 14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
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| D | nuvoton,npcm-pcc.yaml | 14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
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| D | st,stm32u5-msi-clock.yaml | 22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
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| D | st,stm32-msi-clock.yaml | 23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
|
| /Zephyr-latest/drivers/spi/ |
| D | spi_esp32_spim.h | 16 #define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10)
17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
|
| /Zephyr-latest/drivers/modem/ |
| D | Kconfig.hl7800 | 79 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/ |
| D | soc.c | 98 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
114 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
120 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
122 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
126 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
128 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
117 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
119 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
123 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | ti,fdc2x1x.yaml | 46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
100 7 = 33MHz
234 0.01MHz and 8.75MHz
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
236 and 10MHz
240 0.01MHz and 10MHz
|
| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | wch,afio.yaml | 41 default: "max-speed-2mhz"
43 - "max-speed-10mhz"
44 - "max-speed-2mhz"
45 - "max-speed-30mhz"
|
| D | nxp,mcux-rt-pinctrl.yaml | 17 nxp,speed = "100-mhz";
22 slow slew rate, and 100 MHZ speed.
116 10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
142 - "50-mhz"
143 - "100-mhz"
144 - "150-mhz"
145 - "200-mhz"
148 00 SPEED_0_low_50MHz_ — low(50MHz)
149 01 SPEED_1_medium_100MHz_ — medium(100MHz)
150 10 SPEED_2_medium_150MHz_ — medium(150MHz)
[all …]
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| D | st,stm32f1-pinctrl.yaml | 108 default: "max-speed-10mhz"
110 - "max-speed-10mhz" # Default
111 - "max-speed-2mhz"
112 - "max-speed-50mhz"
|
| /Zephyr-latest/drivers/wifi/nrf_wifi/ |
| D | Kconfig.nrfwifi | 236 int "PCB loss for 5 GHz band (5150 MHz - 5350 MHz, Channel-32 - Channel-68)"
245 int "PCB loss for 5 GHz band (5470 MHz - 5730 MHz, Channel-96 - Channel-144)"
254 int "PCB loss for 5 GHz band (5730 MHz - 5895 MHz, Channel-149 - Channel-177)"
268 int "Antenna gain for 5 GHz band (5150 MHz - 5350 MHz)"
273 int "Antenna gain for 5 GHz band (5470 MHz - 5730 MHz)"
278 int "Antenna gain for 5 GHz band (5730 MHz - 5895 MHz)"
285 range 0 10
290 range 0 10
295 range 0 10
300 range 0 10
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| /Zephyr-latest/tests/drivers/pinctrl/gd32/boards/ |
| D | gd32f403z_eval.overlay | 51 pinmux = <GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP)>;
52 slew-rate = "max-speed-2mhz";
56 slew-rate = "max-speed-10mhz";
60 slew-rate = "max-speed-50mhz";
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| D | gd32f450i_eval.overlay | 45 slew-rate = "max-speed-2mhz";
49 slew-rate = "max-speed-25mhz";
53 slew-rate = "max-speed-50mhz";
56 pinmux = <GD32_PINMUX_AF('B', 10, AF10)>;
57 slew-rate = "max-speed-200mhz";
|
| /Zephyr-latest/boards/nxp/mimxrt1010_evk/ |
| D | mimxrt1010_evk-pinctrl.dtsi | 12 /* ADC Channels 1 and 2, exposed as pins 10 and 12 on J26 of EVK */
19 nxp,speed = "100-mhz";
29 nxp,speed = "100-mhz";
42 nxp,speed = "100-mhz";
53 nxp,speed = "100-mhz";
64 nxp,speed = "100-mhz";
70 nxp,speed = "100-mhz";
81 nxp,speed = "100-mhz";
93 nxp,speed = "100-mhz";
99 nxp,speed = "100-mhz";
[all …]
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| /Zephyr-latest/tests/drivers/can/timing/ |
| D | Kconfig | 15 - 10 kbit/s
33 - 20 MHz
34 - 40 MHz
35 - 80 MHz
|
| /Zephyr-latest/dts/bindings/can/ |
| D | ti,tcan4x5x.yaml | 18 bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>;
39 TCAN4x5x oscillator clock frequency in Hz (20MHz or 40MHz).
|
| D | microchip,mcp251xfd.yaml | 46 Enables controller PLL, which multiplies input clock frequency by 10.
65 is not set, then an internal clock (typically 40MHz or 20MHz) will be
71 default: 10
76 - 10
|
| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.spiram | 87 bool "20MHz clock speed"
91 bool "26MHz clock speed"
95 bool "40MHz clock speed"
98 bool "80MHz clock speed"
102 bool "120MHz clock speed"
161 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
169 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
181 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
186 default 10
189 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
[all …]
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| /Zephyr-latest/soc/atmel/sam/sam4l/ |
| D | soc.h | 73 * Internal 80 MHz RC oscillator
74 * Internal 4-8-12 MHz RCFAST oscillator
75 * Internal 1 MHz RC oscillator
91 * 80 MHz RC oscillator
92 * 4-8-12 MHz RC oscillator
93 * 1 MHz RC oscillator
144 #define SYSCLK_USART2 10
205 * 10- ADCIFE
218 #define GEN_CLK_ADCIFE 10
|
| /Zephyr-latest/soc/gd/gd32/common/ |
| D | pinctrl_soc.h | 107 /** Maximum 2MHz */
112 /** Maximum 10MHz */
114 /** Maximum 50MHz */
117 /** Maximum 25MHz */
119 /** Maximum 50MHz */
126 /** Maximum 10MHz */
128 /** Maximum 2MHz */
130 /** Maximum 50MHz */
|
| /Zephyr-latest/boards/nxp/mimxrt1040_evk/ |
| D | mimxrt1040_evk-pinctrl.dtsi | 19 nxp,speed = "100-mhz";
29 nxp,speed = "100-mhz";
33 /* LPI2C1 SDA: J17 pin 9, LPI2C1 SCL: J17 pin 10 */
41 nxp,speed = "100-mhz";
53 nxp,speed = "100-mhz";
66 nxp,speed = "100-mhz";
76 nxp,speed = "100-mhz";
87 nxp,speed = "50-mhz";
93 nxp,speed = "100-mhz";
105 nxp,speed = "100-mhz";
[all …]
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| /Zephyr-latest/boards/nxp/ls1046ardb/ |
| D | ls1046ardb_ls1046a_smp_4cores_defconfig | 6 # 25 MHz system clock
13 CONFIG_MAX_XLAT_TABLES=10
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| D | ls1046ardb_ls1046a_smp_defconfig | 6 # 25 MHz system clock
23 CONFIG_MAX_XLAT_TABLES=10
|
