Lines Matching +full:10 +full:mhz

14       clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15       core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16       apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17       apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18       apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35         120000000, 120 MHz
36         100000000, 100 MHz
37         96000000, 96 MHz
38         90000000, 90 MHz
39         80000000, 80 MHz
40         66000000, 66 MHz
41         50000000, 50 MHz
42         48000000, 48 MHz
59       - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
70         10, CORE_CLK = OFMCLK / 10
81       - 10
89       - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
101         10, APB1_CLK = OFMCLK / 10
112       - 10
120       - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
132         10, APB2_CLK = OFMCLK / 10
143       - 10
151       - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
163         10, APB3_CLK = OFMCLK / 10
174       - 10
181       - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
193         10, APB4_CLK = OFMCLK / 10
204       - 10