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/Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.h7 * SPDX-License-Identifier: Apache-2.0
15 * ---
16 * 1| |5
17 * -2-
19 * ---
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
29 #define CHAR_4 (BIT(1) | BIT(2) | BIT(5) | BIT(6))
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/Zephyr-latest/drivers/sensor/st/lps25hb/
Dlps25hb.h1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7)
34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3)
38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2)
40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1)
41 #define LPS25HB_SHIFT_CTRL_REG1_RESET_AZ 1
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/Zephyr-latest/dts/riscv/ite/
Dit82xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
25 compatible = "ite,it8xxx2-watchdog";
29 interrupt-parent = <&intc>;
32 gpiogcr: gpio-gcr@f03e00 {
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/Zephyr-latest/drivers/sensor/st/lsm9ds0_mfd/
Dlsm9ds0_mfd.h1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer
8 * SPDX-License-Identifier: Apache-2.0
22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
35 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_YMDA 1
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/Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/
Dlsm9ds0_gyro.h1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
32 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_XEN 1
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
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/Zephyr-latest/drivers/audio/
Dtas6422dac.h4 * SPDX-License-Identifier: Apache-2.0
18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
27 /* Miscellaneous Control 1 Register */
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/Zephyr-latest/drivers/sensor/st/lps22hb/
Dlps22hb.h1 /* sensor_lps25hb.h - header file for LPS22HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7)
24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6)
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4)
30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3)
32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2)
34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1)
35 #define LPS22HB_SHIFT_INTERRUPT_CFG_PL_E 1
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/Zephyr-latest/drivers/sensor/st/lsm6ds0/
Dlsm6ds0.h1 /* sensor_lsm6ds0.h - header file for LSM6DS0 accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
23 BIT(0))
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
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/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl.h1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
35 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \
36 BIT(1) | BIT(0))
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
45 BIT(5) | BIT(4) | \
46 BIT(3) | BIT(2) | \
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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
32 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
35 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
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Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
31 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
34 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
39 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
42 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
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/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmi08x-accel.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 int1-map-io:
19 Bit[0]: Map Interrupt A to INT1, Accel Data Ready
20 Bit[1]: Map Interrupt B to INT1
21 Bit[2]: Map Interrupt C to INT1
23 int2-map-io:
26 Bit[0]: Map Interrupt A to INT2, Accel Data Ready
[all …]
Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
25 default: 1
29 1 = 32 V FSR
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
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/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
16 * and as RX on core 1:
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
21 * Message Channel 1 is configured as RX on core 0 and as TX
22 * on core 1:
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
33 IPC_EVENT_BIT(1) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
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/Zephyr-latest/drivers/sensor/apds9960/
Dapds9960.h5 * SPDX-License-Identifier: Apache-2.0
14 #define APDS9960_ENABLE_GEN BIT(6)
15 #define APDS9960_ENABLE_PIEN BIT(5)
16 #define APDS9960_ENABLE_AIEN BIT(4)
17 #define APDS9960_ENABLE_WEN BIT(3)
18 #define APDS9960_ENABLE_PEN BIT(2)
19 #define APDS9960_ENABLE_AEN BIT(1)
20 #define APDS9960_ENABLE_PON BIT(0)
32 #define APDS9960_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
33 #define APDS9960_APERS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dcpu.h3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 * SPDX-License-Identifier: Apache-2.0
16 * SCTLR register bit assignments
18 #define SCTLR_MPU_ENABLE (1 << 0)
30 #define E_BIT (1 << 9)
31 #define A_BIT (1 << 8)
32 #define I_BIT (1 << 7)
33 #define F_BIT (1 << 6)
34 #define T_BIT (1 << 5)
36 #define HIVECS (1 << 13)
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/Zephyr-latest/drivers/i2c/
Di2c_dw_registers.h1 /* i2c_dw_registers.h - array access for I2C Design Ware registers */
6 * SPDX-License-Identifier: Apache-2.0
19 uint32_t master_mode: 1 __packed;
21 uint32_t addr_slave_10bit: 1 __packed;
22 uint32_t addr_master_10bit: 1 __packed;
23 uint32_t restart_en: 1 __packed;
24 uint32_t slave_disable: 1 __packed;
25 uint32_t stop_det: 1 __packed;
26 uint32_t tx_empty_ctl: 1 __packed;
27 uint32_t rx_fifo_full: 1 __packed;
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/Zephyr-latest/drivers/gpio/
Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
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/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dapds9253.h5 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/dt-util.h>
19 #define APDS9253_RESOLUTION_19BIT_200MS BIT(4)
20 #define APDS9253_RESOLUTION_18BIT_100MS BIT(5) /* default */
21 #define APDS9253_RESOLUTION_17BIT_50MS (BIT(5) | BIT(4))
22 #define APDS9253_RESOLUTION_16BIT_25MS BIT(6)
23 #define APDS9253_RESOLUTION_13BIT_3MS (BIT(6) | BIT(4))
32 #define APDS9253_MEASUREMENT_RATE_2000MS (BIT(2) | BIT(1) | BIT(0))
33 #define APDS9253_MEASUREMENT_RATE_1000MS (BIT(2) | BIT(0))
34 #define APDS9253_MEASUREMENT_RATE_500MS BIT(2)
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/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dnuclei_csr.h5 * SPDX-License-Identifier: Apache-2.0
13 * Use arch/riscv/csr.h for RISC-V standard CSR and definitions.
31 #define MCOUNTINHIBIT_IR BIT(2U)
32 #define MCOUNTINHIBIT_CY BIT(0U)
34 #define MILM_CTL_ILM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
35 #define MILM_CTL_ILM_RWECC BIT(3U)
36 #define MILM_CTL_ILM_ECC_EXCP_EN BIT(2U)
37 #define MILM_CTL_ILM_ECC_EN BIT(1U)
38 #define MILM_CTL_ILM_EN BIT(0U)
40 #define MDLM_CTL_DLM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
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/Zephyr-latest/include/zephyr/drivers/mfd/
Dmax31790.h3 * SPDX-License-Identifier: Apache-2.0
13 #define MAX31790_PWMTARGETDUTYCYCLE_MAXIMUM ((1 << 9) - 1)
14 #define MAX31790_TACHTARGETCOUNT_MAXIMUM ((1 << 11) - 1)
27 #define MAX37190_GLOBALCONFIGURATION_STANDBY_BIT BIT(7)
28 #define MAX37190_GLOBALCONFIGURATION_RESET_BIT BIT(6)
29 #define MAX37190_GLOBALCONFIGURATION_BUSTIMEOUT_BIT BIT(5)
30 #define MAX37190_GLOBALCONFIGURATION_OSCILLATORSELECTION_BIT BIT(3)
31 #define MAX37190_GLOBALCONFIGURATION_I2CWATCHDOGSTATUS_BIT BIT(0)
32 #define MAX37190_FANXCONFIGURATION_MONITOR_BIT BIT(4)
33 #define MAX37190_FANXCONFIGURATION_TACHINPUTENABLED_BIT BIT(3)
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_gecko_priv.h5 * SPDX-License-Identifier: Apache-2.0
29 #define ETH_TX_USED BIT(31)
30 #define ETH_TX_WRAP BIT(30)
31 #define ETH_TX_ERROR BIT(29)
32 #define ETH_TX_UNDERRUN BIT(28)
33 #define ETH_TX_EXHAUSTED BIT(27)
34 #define ETH_TX_NO_CRC BIT(16)
35 #define ETH_TX_LAST BIT(15)
36 #define ETH_TX_LENGTH (2048-1)
38 #define ETH_RX_ADDRESS ~(ETH_DESC_ALIGNMENT-1)
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/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_kbc.h4 * SPDX-License-Identifier: Apache-2.0
13 /* ---- EM8042 Keyboard Controller (KBC) ---- */
15 /* EC_KBC_STS and KBC_STS_RD bit definitions */
17 #define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS)
18 #define MCHP_KBC_STS_IBF_POS 1u
19 #define MCHP_KBC_STS_IBF BIT(MCHP_KBC_STS_IBF_POS)
21 #define MCHP_KBC_STS_UD0 BIT(MCHP_KBC_STS_UD0_POS)
23 #define MCHP_KBC_STS_CD BIT(MCHP_KBC_STS_CD_POS)
25 #define MCHP_KBC_STS_UD1 BIT(MCHP_KBC_STS_UD1_POS)
27 #define MCHP_KBC_STS_AUXOBF BIT(MCHP_KBC_STS_AUXOBF_POS)
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_mcr20a_regs.h1 /* ieee802154_mcr20a_regs.h - Registers definition for NXP MCR20A */
6 * SPDX-License-Identifier: Apache-2.0
11 * which are used in the macros for the bit field manipulation.
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
93 /* ---------------- (0x27) */
112 /* ---------------- (0x3a) */
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