Lines Matching +full:1 +full:- +full:bit

5  * SPDX-License-Identifier: Apache-2.0
13  * Use arch/riscv/csr.h for RISC-V standard CSR and definitions.
31 #define MCOUNTINHIBIT_IR            BIT(2U)
32 #define MCOUNTINHIBIT_CY            BIT(0U)
34 #define MILM_CTL_ILM_BPA            (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
35 #define MILM_CTL_ILM_RWECC          BIT(3U)
36 #define MILM_CTL_ILM_ECC_EXCP_EN    BIT(2U)
37 #define MILM_CTL_ILM_ECC_EN         BIT(1U)
38 #define MILM_CTL_ILM_EN             BIT(0U)
40 #define MDLM_CTL_DLM_BPA            (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
41 #define MDLM_CTL_DLM_RWECC          BIT(3U)
42 #define MDLM_CTL_DLM_ECC_EXCP_EN    BIT(2U)
43 #define MDLM_CTL_DLM_ECC_EN         BIT(1U)
44 #define MDLM_CTL_DLM_EN             BIT(0U)
51 #define MMISC_CTL_NMI_CAUSE_FFF     BIT(9U)
52 #define MMISC_CTL_MISALIGN          BIT(6U)
53 #define MMISC_CTL_BPu               BIT(3U)
55 #define MCACHE_CTL_IC_EN            BIT(0U)
56 #define MCACHE_CTL_IC_SCPD_MOD      BIT(1U)
57 #define MCACHE_CTL_IC_ECC_EN        BIT(2U)
58 #define MCACHE_CTL_IC_ECC_EXCP_EN   BIT(3U)
59 #define MCACHE_CTL_IC_RWTECC        BIT(4U)
60 #define MCACHE_CTL_IC_RWDECC        BIT(5U)
61 #define MCACHE_CTL_DC_EN            BIT(16U)
62 #define MCACHE_CTL_DC_ECC_EN        BIT(17U)
63 #define MCACHE_CTL_DC_ECC_EXCP_EN   BIT(18U)
64 #define MCACHE_CTL_DC_RWTECC        BIT(19U)
65 #define MCACHE_CTL_DC_RWDECC        BIT(20U)
67 #define MTVT2_MTVT2EN               BIT(0U)
68 #define MTVT2_COMMON_CODE_ENTRY     (((1ULL << ((__riscv_xlen) - 2U)) - 1U) << 2U)
70 #define MCFG_INFO_TEE               BIT(0U)
71 #define MCFG_INFO_ECC               BIT(1U)
72 #define MCFG_INFO_CLIC              BIT(2U)
73 #define MCFG_INFO_PLIC              BIT(3U)
74 #define MCFG_INFO_FIO               BIT(4U)
75 #define MCFG_INFO_PPI               BIT(5U)
76 #define MCFG_INFO_NICE              BIT(6U)
77 #define MCFG_INFO_ILM               BIT(7U)
78 #define MCFG_INFO_DLM               BIT(8U)
79 #define MCFG_INFO_ICACHE            BIT(9U)
80 #define MCFG_INFO_DCACHE            BIT(10U)
97 #define MPPICFG_INFO_PPI_SIZE       (0x1FU << 1U)
98 #define MPPICFG_INFO_PPI_BPA        (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
100 #define MFIOCFG_INFO_FIO_SIZE       (0x1FU << 1)
101 #define MFIOCFG_INFO_FIO_BPA        (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
120 #define FFLAGS_AE_NX                BIT(0U)
121 #define FFLAGS_AE_UF                BIT(1U)
122 #define FFLAGS_AE_OF                BIT(2U)
123 #define FFLAGS_AE_DZ                BIT(3U)
124 #define FFLAGS_AE_NV                BIT(4U)
131 #define RISCV_PGSIZE                (1U << RISCV_PGSHIFT)