Lines Matching +full:1 +full:- +full:bit
1 /* i2c_dw_registers.h - array access for I2C Design Ware registers */
6 * SPDX-License-Identifier: Apache-2.0
19 uint32_t master_mode: 1 __packed;
21 uint32_t addr_slave_10bit: 1 __packed;
22 uint32_t addr_master_10bit: 1 __packed;
23 uint32_t restart_en: 1 __packed;
24 uint32_t slave_disable: 1 __packed;
25 uint32_t stop_det: 1 __packed;
26 uint32_t tx_empty_ctl: 1 __packed;
27 uint32_t rx_fifo_full: 1 __packed;
33 #define IC_DATA_CMD_CMD BIT(8)
34 #define IC_DATA_CMD_STOP BIT(9)
35 #define IC_DATA_CMD_RESTART BIT(10)
38 #define DW_INTR_STAT_RX_UNDER BIT(0)
39 #define DW_INTR_STAT_RX_OVER BIT(1)
40 #define DW_INTR_STAT_RX_FULL BIT(2)
41 #define DW_INTR_STAT_TX_OVER BIT(3)
42 #define DW_INTR_STAT_TX_EMPTY BIT(4)
43 #define DW_INTR_STAT_RD_REQ BIT(5)
44 #define DW_INTR_STAT_TX_ABRT BIT(6)
45 #define DW_INTR_STAT_RX_DONE BIT(7)
46 #define DW_INTR_STAT_ACTIVITY BIT(8)
47 #define DW_INTR_STAT_STOP_DET BIT(9)
48 #define DW_INTR_STAT_START_DET BIT(10)
49 #define DW_INTR_STAT_GEN_CALL BIT(11)
50 #define DW_INTR_STAT_RESTART_DET BIT(12)
51 #define DW_INTR_STAT_MST_ON_HOLD BIT(13)
53 #define DW_INTR_MASK_RX_UNDER BIT(0)
54 #define DW_INTR_MASK_RX_OVER BIT(1)
55 #define DW_INTR_MASK_RX_FULL BIT(2)
56 #define DW_INTR_MASK_TX_OVER BIT(3)
57 #define DW_INTR_MASK_TX_EMPTY BIT(4)
58 #define DW_INTR_MASK_RD_REQ BIT(5)
59 #define DW_INTR_MASK_TX_ABRT BIT(6)
60 #define DW_INTR_MASK_RX_DONE BIT(7)
61 #define DW_INTR_MASK_ACTIVITY BIT(8)
62 #define DW_INTR_MASK_STOP_DET BIT(9)
63 #define DW_INTR_MASK_START_DET BIT(10)
64 #define DW_INTR_MASK_GEN_CALL BIT(11)
65 #define DW_INTR_MASK_RESTART_DET BIT(12)
66 #define DW_INTR_MASK_MST_ON_HOLD BIT(13)
72 uint32_t rx_under: 1 __packed;
73 uint32_t rx_over: 1 __packed;
74 uint32_t rx_full: 1 __packed;
75 uint32_t tx_over: 1 __packed;
76 uint32_t tx_empty: 1 __packed;
77 uint32_t rd_req: 1 __packed;
78 uint32_t tx_abrt: 1 __packed;
79 uint32_t rx_done: 1 __packed;
80 uint32_t activity: 1 __packed;
81 uint32_t stop_det: 1 __packed;
82 uint32_t start_det: 1 __packed;
83 uint32_t gen_call: 1 __packed;
84 uint32_t restart_det: 1 __packed;
85 uint32_t mst_on_hold: 1 __packed;
95 uint32_t gc_or_start: 1 __packed;
96 uint32_t special: 1 __packed;
97 uint32_t ic_10bitaddr_master: 1 __packed;
108 uint32_t hc_count_values: 1 __packed;
109 uint32_t intr_io: 1 __packed;
110 uint32_t has_dma: 1 __packed;
111 uint32_t add_encoded_params: 1 __packed;
158 /* CON Bit */
162 #define DW_IC_DMA_RX_ENABLE BIT(0)
163 #define DW_IC_DMA_TX_ENABLE BIT(1)
164 #define DW_IC_DMA_ENABLE (BIT(0) | BIT(1))
211 #define DW_IC_STATUS_TFNT_BIT (1)