Lines Matching +full:1 +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
39 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
42 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
54 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
55 #define SSCR0_EFRDC BIT(27)
56 #define SSCR0_EFRDC2 BIT(28)
58 #define SSCR0_ACS BIT(30)
59 #define SSCR0_MOD BIT(31)
62 #define SSCR1_RIE BIT(0)
63 #define SSCR1_TIE BIT(1)
64 #define SSCR1_LBM BIT(2)
66 #define SSCR1_IFS BIT(16)
67 #define SSCR1_PINTE BIT(18)
68 #define SSCR1_TINTE BIT(19)
70 #define SSCR1_TRAIL BIT(22)
71 #define SSCR1_RWOT BIT(23)
72 #define SSCR1_SFRMDIR BIT(24)
73 #define SSCR1_SCLKDIR BIT(25)
74 #define SSCR1_SCFR BIT(28)
75 #define SSCR1_EBCEI BIT(29)
76 #define SSCR1_TTE BIT(30)
77 #define SSCR1_TTELP BIT(31)
79 #define SSCR2_TURM1 BIT(1)
80 #define SSCR2_PSPSRWFDFD BIT(3)
81 #define SSCR2_PSPSTWFDFD BIT(4)
82 #define SSCR2_SDFD BIT(14)
83 #define SSCR2_SDPM BIT(16)
84 #define SSCR2_LJDFD BIT(17)
85 #define SSCR2_MMRATF BIT(18)
86 #define SSCR2_SMTATF BIT(19)
87 #define SSCR2_SFRMEN BIT(20)
88 #define SSCR2_ACIOLBS BIT(21)
91 #define SSSR_BSY BIT(4)
92 #define SSSR_ROR BIT(7)
93 #define SSSR_TUR BIT(21)
96 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x)
104 #define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
105 #define SSPSP_FSRT BIT(25)
130 #define SSCR3_FRM_MST_EN BIT(0)
131 #define SSCR3_I2S_MODE_EN BIT(1)
133 #define SSCR3_I2S_TX_SS_FIX_EN BIT(3)
134 #define SSCR3_I2S_RX_SS_FIX_EN BIT(4)
135 #define SSCR3_I2S_TX_EN BIT(9)
136 #define SSCR3_I2S_RX_EN BIT(10)
137 #define SSCR3_CLK_EDGE_SEL BIT(12)
138 #define SSCR3_STRETCH_TX BIT(14)
139 #define SSCR3_STRETCH_RX BIT(15)
140 #define SSCR3_MST_CLK_EN BIT(16)
141 #define SSCR3_SYN_FIX_EN BIT(17)
147 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
151 #define SFIFOTT_TX(x) ((x) - 1)
152 #define SFIFOTT_RX(x) (((x) - 1) << 16)
158 #define SSTSA_TSEN BIT(8)
159 #define SSRSA_RSEN BIT(8)
165 #define SSCR3_TX(x) DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
166 #define SSCR3_RX(x) DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
168 #define SSIOC_TXDPDEB BIT(1)
169 #define SSIOC_SFCR BIT(4)
170 #define SSIOC_SCOE BIT(5)
173 #define SSMIDyCS_RXEN BIT(0)
174 #define SSMIDyCS_RSRE BIT(1)
177 #define SSMIDyCS_RNE BIT(26)
178 #define SSMIDyCS_RFS BIT(27)
179 #define SSMIDyCS_ROR BIT(28)
180 #define SSMIDyCS_PINT BIT(29)
181 #define SSMIDyCS_TINT BIT(30)
182 #define SSMIDyCS_EOC BIT(31)
189 #define SSMODyCS_TXEN BIT(0)
190 #define SSMODyCS_TSRE BIT(1)
193 #define SSMODyCS_TNF BIT(26)
194 #define SSMODyCS_TFS BIT(27)
195 #define SSMODyCS_TUR BIT(28)
207 #define SSP_CLK_MCLK_ES_REQ BIT(0)
208 #define SSP_CLK_MCLK_ACTIVE BIT(1)
209 #define SSP_CLK_BCLK_ES_REQ BIT(2)
210 #define SSP_CLK_BCLK_ACTIVE BIT(3)
214 #define I2SLCTL_OFLEN BIT(4)
215 #define I2SLCTL_SPA(x) BIT(16 + x)
216 #define I2SLCTL_CPA(x) BIT(23 + x)
220 #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
221 #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x)
230 #define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)