1 /*
2  * Copyright (c) 2018 Lexmark International, Inc.
3  * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_
9 #define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_
10 
11 #if defined(CONFIG_ARM_MPU)
12 #include <zephyr/arch/arm/cortex_a_r/mpu.h>
13 #endif
14 
15 /*
16  * SCTLR register bit assignments
17  */
18 #define SCTLR_MPU_ENABLE	(1 << 0)
19 
20 #define MODE_USR	0x10
21 #define MODE_FIQ	0x11
22 #define MODE_IRQ	0x12
23 #define MODE_SVC	0x13
24 #define MODE_ABT	0x17
25 #define MODE_HYP	0x1a
26 #define MODE_UND	0x1b
27 #define MODE_SYS	0x1f
28 #define MODE_MASK	0x1f
29 
30 #define E_BIT	(1 << 9)
31 #define A_BIT	(1 << 8)
32 #define I_BIT	(1 << 7)
33 #define F_BIT	(1 << 6)
34 #define T_BIT	(1 << 5)
35 
36 #define HIVECS	(1 << 13)
37 
38 #define CPACR_NA	(0U)
39 #define CPACR_FA	(3U)
40 
41 #define CPACR_CP10(r)	(r << 20)
42 #define CPACR_CP11(r)	(r << 22)
43 
44 #define FPEXC_EN	(1 << 30)
45 
46 #define DFSR_DOMAIN_SHIFT	(4)
47 #define DFSR_DOMAIN_MASK	(0xf)
48 #define DFSR_FAULT_4_MASK	(1 << 10)
49 #define DFSR_WRITE_MASK		(1 << 11)
50 #define DFSR_AXI_SLAVE_MASK	(1 << 12)
51 
52 /* Armv8-R AArch32 architecture profile */
53 #define VBAR_MASK		(0xFFFFFFE0U)
54 #define SCTLR_M_BIT		BIT(0)
55 #define SCTLR_A_BIT		BIT(1)
56 #define SCTLR_C_BIT		BIT(2)
57 #define SCTLR_I_BIT		BIT(12)
58 
59 /* Armv8-R Cortex-R52 Cache Segregation Control Register */
60 #define IMP_CSCTLR_DFLW_SHIFT	(0)
61 #define IMP_CSCTLR_IFLW_SHIFT	(8)
62 #define IMP_CSCTLR(iway, dway)  ((iway << IMP_CSCTLR_IFLW_SHIFT) | \
63 				((dway << IMP_CSCTLR_DFLW_SHIFT)))
64 
65 /* Hyp System Control Register */
66 #define HSCTLR_RES1		(BIT(29) | BIT(28) | BIT(23) | \
67 				 BIT(22) | BIT(18) | BIT(16) | \
68 				 BIT(11) | BIT(4)  | BIT(3))
69 
70 /* Hyp Auxiliary Control Register */
71 #define HACTLR_CPUACTLR         BIT(0)
72 #define HACTLR_CDBGDCI          BIT(1)
73 #define HACTLR_FLASHIFREGIONR   BIT(7)
74 #define HACTLR_PERIPHPREGIONR   BIT(8)
75 #define HACTLR_QOSR_BIT         BIT(9)
76 #define HACTLR_BUSTIMEOUTR_BIT  BIT(10)
77 #define HACTLR_INTMONR_BIT      BIT(12)
78 #define HACTLR_ERR_BIT          BIT(13)
79 
80 #define HACTLR_INIT (HACTLR_ERR_BIT | HACTLR_INTMONR_BIT | \
81 		     HACTLR_BUSTIMEOUTR_BIT | HACTLR_QOSR_BIT | \
82 		     HACTLR_PERIPHPREGIONR | HACTLR_FLASHIFREGIONR | \
83 		     HACTLR_CDBGDCI | HACTLR_CPUACTLR)
84 /* ARMv8 Timer */
85 #define CNTV_CTL_ENABLE_BIT	BIT(0)
86 #define CNTV_CTL_IMASK_BIT	BIT(1)
87 
88 /* Interrupt Controller System Register Enable Register */
89 #define ICC_SRE_ELx_SRE_BIT	BIT(0)
90 #define ICC_SRE_ELx_DFB_BIT	BIT(1)
91 #define ICC_SRE_ELx_DIB_BIT	BIT(2)
92 #define ICC_SRE_EL3_EN_BIT	BIT(3)
93 
94 /* MPIDR mask to extract Aff0, Aff1, and Aff2 */
95 #define MPIDR_AFFLVL_MASK (0xffffff)
96 
97 #define MPIDR_AFF0_SHIFT	(0)
98 #define MPIDR_AFF1_SHIFT	(8)
99 #define MPIDR_AFF2_SHIFT	(16)
100 
101 #define MPIDR_AFFLVL(mpidr, aff_level) \
102 		(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
103 
104 #define GET_MPIDR()		read_sysreg(mpidr)
105 #define MPIDR_TO_CORE(mpidr)	MPIDR_AFFLVL(mpidr, 0)
106 
107 /* ICC SGI macros */
108 #define SGIR_TGT_MASK		(0xffff)
109 #define SGIR_AFF1_SHIFT		(16)
110 #define SGIR_AFF2_SHIFT		(32)
111 #define SGIR_AFF3_SHIFT		(48)
112 #define SGIR_AFF_MASK		(0xff)
113 #define SGIR_INTID_SHIFT	(24)
114 #define SGIR_INTID_MASK		(0xf)
115 #define SGIR_IRM_SHIFT		(40)
116 #define SGIR_IRM_MASK		(0x1)
117 #define SGIR_IRM_TO_AFF		(0)
118 
119 #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt)	\
120 	((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) |	\
121 	 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) |	\
122 	 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) |	\
123 	 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) |		\
124 	 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) |		\
125 	 ((_tgt) & SGIR_TGT_MASK))
126 
127 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_ */
128