Lines Matching +full:1 +full:- +full:bit

4  * SPDX-License-Identifier: Apache-2.0
13 /* ---- EM8042 Keyboard Controller (KBC) ---- */
15 /* EC_KBC_STS and KBC_STS_RD bit definitions */
17 #define MCHP_KBC_STS_OBF	BIT(MCHP_KBC_STS_OBF_POS)
18 #define MCHP_KBC_STS_IBF_POS	1u
19 #define MCHP_KBC_STS_IBF	BIT(MCHP_KBC_STS_IBF_POS)
21 #define MCHP_KBC_STS_UD0	BIT(MCHP_KBC_STS_UD0_POS)
23 #define MCHP_KBC_STS_CD		BIT(MCHP_KBC_STS_CD_POS)
25 #define MCHP_KBC_STS_UD1	BIT(MCHP_KBC_STS_UD1_POS)
27 #define MCHP_KBC_STS_AUXOBF	BIT(MCHP_KBC_STS_AUXOBF_POS)
32 #define MCHP_KBC_STS_UD2_0	BIT(6)
33 #define MCHP_KBC_STS_UD2_1	BIT(7)
35 /* KBC_CTRL bit definitions */
37 #define MCHP_KBC_CTRL_UD3		BIT(MCHP_KBC_CTRL_UD3_POS)
38 #define MCHP_KBC_CTRL_SAEN_POS		1u
39 #define MCHP_KBC_CTRL_SAEN		BIT(MCHP_KBC_CTRL_SAEN_POS)
41 #define MCHP_KBC_CTRL_PCOBFEN		BIT(MCHP_KBC_CTRL_PCOBFEN_POS)
46 #define MCHP_KBC_CTRL_OBFEN		BIT(MCHP_KBC_CTRL_OBFEN_POS)
48 #define MCHP_KBC_CTRL_UD5		BIT(MCHP_KBC_CTRL_UD5_POS)
50 #define MCHP_KBC_CTRL_AUXH		BIT(MCHP_KBC_CTRL_AUXH_POS)
52 /* PCOBF register bit definitions */
54 #define MCHP_KBC_PCOBF_EN	BIT(MCHP_KBC_PCOBF_EN_POS)
56 /* KBC_PORT92_EN register bit definitions */
58 #define MCHP_KBC_PORT92_EN	BIT(MCHP_KBC_PORT92_EN_POS)
61 #define MCHP_PORT92_HOST_MASK			GENMASK(1, 0)
63 #define MCHP_PORT92_HOST_ALT_CPU_RST		BIT(0)
64 #define MCHP_PORT92_HOST_ALT_GA20_POS		1
65 #define MCHP_PORT92_HOST_ALT_GA20		BIT(1)
68 #define MCHP_PORT92_GA20_CTRL_MASK	BIT(0)
70 #define MCHP_PORT92_GA20_CTRL_VAL_HI	BIT(0)
73  * SETGA20L - writes of any data to this register causes
76 #define MCHP_PORT92_SETGA20L_MASK	BIT(0)
78 #define MCHP_PORT92_SETGA20L_SET	BIT(0)
81  * RSTGA20L - writes of any data to this register causes
84 #define MCHP_PORT92_RSTGA20L_MASK	BIT(0)
86 #define MCHP_PORT92_RSTGA20L_RST	BIT(0)
89 #define MCHP_PORT92_ACTV_MASK		BIT(0)
90 #define MCHP_PORT92_ACTV_ENABLE		BIT(0)
96 	uint8_t RSVD1[0x100 - 0x08];
101 	uint32_t RSVD2[1];
103 	uint8_t RSVD3[0x0330 - 0x0118];
110 	uint8_t RSVD1[0x100u - 0x04u];
112 	uint32_t RSVD2[1];
115 	uint8_t RSVD3[0x0330ul - 0x0110ul];